PSD4235G2V-10UI datasheet(32/100 Pages) STMICROELECTRONICS

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PSD4256G6V

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Data Toggle

Checking the Toggle Flag Bit (DQ6/DQ14) is an-

other method of determining whether a Program or

Erase cycle is in progress or has completed. Fig-

ure 7 shows the Data Toggle algorithm.

When the MCU issues a Program instruction, the

embedded algorithm within the PSD begins. The

MCU then reads the location to be programmed in

Flash memory to check the status. The Toggle

Flag Bit (DQ6/DQ14) toggles each time the MCU

reads this location until the embedded algorithm is

complete. The MCU continues to read this loca-

tion, checking the Toggle Flag Bit (DQ6/DQ14)

and monitoring the Error Flag Bit (DQ5/DQ13).

When the Toggle Flag Bit (DQ6/DQ14) stops tog-

gling (two consecutive READs yield the same val-

ue), and the Error Flag Bit (DQ5/DQ13) remains

’0,’ the embedded algorithm is complete. If the Er-

ror Flag Bit (DQ5/DQ13) is ’1,’ the MCU should

test the Toggle Flag Bit (DQ6/DQ14) again, since

the Toggle Flag Bit (DQ6/DQ14) may have

changed simultaneously with the Error Flag Bit

(DQ5/DQ13) (see Figure 7).

The Error Flag Bit (DQ5/DQ13) is set if either an

internal time-out occurred while the embedded al-

gorithm attempted to program, or if the MCU at-

tempted to program a ’1’ to a bit that was not

erased (not erased is logic ’0’).

It is suggested (as with all Flash memories) to read

the location again after the embedded program-

ming algorithm has completed, to compare the

word that was written to Flash memory with the

word that was intended to be written.

When using the Data Toggle method after an

Erase cycle, Figure 7 still applies. the Toggle Flag

Bit (DQ6/DQ14) toggles until the Erase cycle is

complete. A ’1’ on the Error Flag Bit (DQ5/DQ13)

indicates a time-out condition on the Erase cycle,

a ’0’ indicates no error. The MCU can read any

even location within the sector being erased to get

the Toggle Flag Bit (DQ6/DQ14) and the Error

Flag Bit (DQ5/DQ13).

PSDsoft generates ANSI C code functions which

implement these Data Toggling algorithms.

Unlock Bypass

The Unlock Bypass instruction allows the system

to program words to the Flash memories faster

than using the standard Program instruction. The

Unlock Bypass mode is entered by first initiating

two Unlock cycles. This is followed by a third

WRITE cycle containing the Unlock Bypass com-

mand, 20h (as shown in Table 29, page 27). The

Flash memory then enters the Unlock Bypass

mode.

A two-cycle Unlock Bypass Program instruction is

all that is required to program in this mode. The

first cycle in this instruction contains the Unlock

Bypass Program command, A0h. The second cy-

cle contains the program address and data. Addi-

tional data is programmed in the same manner.

This mode dispense with the initial two Unlock cy-

cles required in the standard Program instruction,

resulting in faster total programming time.

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset in-

structions are valid.

To exit the Unlock Bypass mode, the system must

issue the two-cycle Unlock Bypass Reset instruc-

tion. The first cycle must contain the data 90h; the

second cycle the data 00h. Addresses are “Don’t

care” for both cycles. The Flash memory then re-

turns to READ Mode.

Figure 7. Data Toggle Flowchart

START

READ DQ6

(DQ14)

AI04921

Yes

Program

or Erase

Cycle failed

Program

or Erase

Cycle is

complete

Issue RESET

instruction

READ DQ5 and DQ6

(DQ13 and DQ14)

at Valid Even Address

DQ5

(DQ13)

= 1

DQ6

(DQ14)

Toggle

DQ6

(DQ14)

Toggle

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