PSD4235G2V-10UI datasheet(55/100 Pages) STMICROELECTRONICS

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PSD4256G6V

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

MMC2001

The Motorola MCORE MMC2001 MCU has a

MOD input pin that selects internal or external boot

ROM. The PSD can be configured as the external

flash boot ROM or as extension to the internal

ROM (see Figure 25, page 56).

The MMC2001 has a 16-bit external data bus and

20 address lines with external chip select signals.

The Chip Select Control Registers allow the user

to customize the bus interface and timing to fit the

individual system requirement. A typical interface

configuration to the PSD is shown in Figure 25,

page 56. The MMC2001’s R/W signal is connect-

ed to the CNTL0 pin, while EB0 and EB1 (enable

byte-0 and enable byte-1) are connected to the

CNTL1 (UDS) and CNTL2 (LDS) pins. The WEN

bit in the Chip Select Control Register should be

set to 1 to terminate the EB0-EB1 earlier to pro-

vide the write data hold time for the PSD. The

WSC and WWS bits in the Control Register are set

to wait states that meet the PSD access time re-

quirement.

Another option is to configure the EB0 and EB1 as

WRL and WRH signals. In this case, the PSD con-

trol setting will be: OE, WRL, WRH where OE is

the READ signal for the MMC2001.

C16x Family

The PSD supports Infineon’s C16X family of

MCUs (C161-C167) in both the multiplexed and

non-multiplexed bus configuration. In Figure 26,

page 57, the C167CR is shown connected to the

PSD in a multiplexed bus configuration. The con-

trol signals from the MCU are WR, RD, BHE and

ALE, and are routed to the corresponding PSD

pins.

The C167 has another control signal setting (RD,

WRL, WRH, ALE) which is also supported by the

PSD.

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