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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD4235G2V-10UI датащи(PDF) 64 Page - STMicroelectronics |
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PSD4235G2V-10UI датащи(HTML) 64 Page - STMicroelectronics |
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64 / 100 page  PSD4256G6V 64/100 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Direction Register The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to 1 in the Di- rection Register causes the corresponding pin to be an output, and any bit set to 0 causes it to be an input. The default mode for all port pins is input. Figure 28, page 62 and Figure 30, page 67 show the Port Architecture diagrams for Ports A/B/C and E/F/G, respectively. The direction of data flow for Ports A, B, C and F are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the out- put enable product term is not active, the Direction Register has sole control of a given pin’s direction. An example of a configuration for a Port with the three least significant bits set to output and the re- mainder set to input is shown in Table 45. Since Port D only contains four pins, the Direction Reg- ister for Port D has only the four least significant bits active. Drive Select Register The Drive Select Register configures the pin driver as Open Drain or CMOS. An external pull-up resis- tor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corre- sponding bit in the Drive Select Register is set to a 1. The default pin drive is CMOS. Table 46 shows the Drive Register for Ports A, B, D, E and G. It summarizes which pins can be con- figured as Open Drain outputs. Table 43. Port Pin Direction Control, Output Enable P.T. Not Defined Table 44. Port Pin Direction Control, Output Enable P.T. Defined Table 45. Port Direction Assignment Example Table 46. Drive Register Pin Assignment Note: 1. NA = Not Applicable. Direction Register Bit Port Pin Mode 0 Input 1 Output Direction Register Bit Output Enable P.T. Port Pin Mode 0 0 Input 0 1 Output 1 0 Output 1 1 Output Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 1 1 1 Drive Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port A Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Port B Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Port D NA(1) NA(1) NA(1) NA(1) Open Drain Open Drain Open Drain Open Drain Port E Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Port G Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain |
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