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PSD4235G2V-10UI датащи(PDF) 89 Page - STMicroelectronics |
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PSD4235G2V-10UI датащи(HTML) 89 Page - STMicroelectronics |
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89 / 100 page ![]() 89/100 PSD4256G6V This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Table 66. READ Timing Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 2. Any input used to select an internal PSD function. 3. In multiplexed mode latched address generated from ADIO delay to address output on any Port. 4. RD timing has the same timing as DS, LDS, and UDS signals. Symbol Parameter Conditions -10 Turbo Off Unit Min Max tLVLX ALE or AS Pulse Width 22 ns tAVLX Address Setup Time (Note 2) 7ns tLXAX Address Hold Time (Note 2) 8ns tAVQV Address Valid to Data Valid 2.7 < VCC < 3.6V (Note 2) 100 + 20 ns 3.0 < VCC < 3.6V (Note 2) 90 + 20 ns tSLQV CS Valid to Data Valid 100 ns tRLQV RD to Data Valid (Note 3) 35 ns RD or PSEN to Data Valid on 80C51XA 45 ns tRHQX RD Data Hold Time (Note 1) 0ns tRLRH RD Pulse Width 36 ns tRHQZ RD to Data High-Z (Note 1) 38 ns tEHEL E Pulse Width 38 ns tTHEH R/W Setup Time to Enable 10 ns tELTL R/W Hold Time After Enable 0 ns tAVPV Address Input Valid to Address Output Delay (Note 3) 35 ns |
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