PSD4235G2V-10UI datasheet(93/100 Pages) STMICROELECTRONICS

93 / 100 page

93/100

PSD4256G6V

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Table 69. Port F Peripheral Data Mode WRITE Timing

Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).

2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.

3. Any input used to select Port F Data Peripheral mode.

4. Data is already stable on Port F.

5. Data stable on ADIO pins to data on Port F.

Table 70. Power-down Timing

Table 71. Reset (RESET) Timing

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Figure 48. Reset (RESET) Timing Diagram

Table 72. VSTBYON Timing

Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.

Symbol

Parameter

Conditions

-10

Unit

Min

Max

tWLQV–PF

WR to Data Propagation Delay

(Note 2)

tDVQV–PF

Data to Port A Data Propagation Delay

(Note 5)

tWHQZ–PF

WR Invalid to Port A Tri-state

(Note 2)

Symbol

Parameter

Conditions

-10

Unit

Min

Max

tLVDV

ALE Access Time from Power-down

128

tCLWH

Maximum Delay from APD Enable to

Internal PDN Valid Signal

Using CLKIN

(PD1)

15 * tCLCL

µs

Symbol

Parameter

Conditions

Min

Max

Unit

tNLNH

RESET Active Low Time 1

300

tNLNH–PO

Power-on RESET Active Low Time

tNLNH–A

Warm RESET Active Low Time 2

µs

tOPR

RESET High to Operational Device

300

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tBVBH

VSTBY Detection to VSTBYON Output High

(Note 1)

µs

tBXBL

VSTBY Off Detection to VSTBYON Output

Low

(Note 1)

µs

tNLNH-PO

tOPR

AI02866b

RESET

tNLNH

tNLNH-A

tOPR

VCC

CC(min)

Power-On Reset

Warm Reset

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