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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD4235G2V-10UI датащи(PDF) 67 Page - STMicroelectronics |
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PSD4235G2V-10UI датащи(HTML) 67 Page - STMicroelectronics |
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67 / 100 page  67/100 PSD4256G6V This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Port D – Functionality and Structure Port D has four I/O pins. See Figure 30. Port D can be configured to perform one or more of the follow- ing functions: s MCU I/O mode s CPLD Input – direct input to the CPLD, no Input Macrocells (IMC) Port D pins can be configured in PSDsoft as in- put pins for other dedicated functions: s Address Strobe (ALE/AS, PD0) s CLKIN (PD1) as input to the Macrocells Flip- flops and APD counter s PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory, SRAM and CSIOP. s WRITE-Enable High-byte (WRH, PD3) input, or as DBE input from a MC68HC912. Figure 30. Port D Structure DATA OUT Register DQ DQ WR WR READ MUX P D B CPLD - INPUT DIR Register DATA IN OUTPUT SELECT OUTPUT MUX PORT D PIN DATA OUT AI04937 |
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