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PSD4235G2V-10UI датащи(PDF) 66 Page - STMicroelectronics

номер детали PSD4235G2V-10UI
подробное описание детали  Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
PDF  100 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD4235G2V-10UI датащи(HTML) 66 Page - STMicroelectronics

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Enable Out
The Enable Out register can be read by the MCU.
It contains the output enable values for a given
port. A 1 indicates the driver is in output mode. A
0 indicates the driver is in tri-state and the pin is in
input mode.
Ports A, B and C – Functionality and Structure
Ports A, B, and C have similar functionality and
structure, as shown in Figure 29. The ports can be
configured to perform one or more of the following
functions:
s
MCU I/O Mode
s
CPLD Output – Macrocells McellA7-McellA0
can be connected to Port A. McellB7-McellB0
can be connected to Port B. External Chip
Select (ECS7-ECS0) can be connected to Port
C or Port F.
s
CPLD Input – Via the Input Macrocells (IMC).
s
Address In – Additional high address inputs
using the Input Macrocells (IMC).
s
Open Drain – pins PA7-PA0 can be configured
to Open Drain mode.
Figure 29. Port A, B, and C Structure
DATA OUT
Register
DQ
DQ
WR
WR
MCELLA7-MCELLA0 (Port A)
MCELLB7-MCELLB0 (Port B)
Ext.CS (Port C)
ENABLE PRODUCT TERM (.OE)
READ MUX
P
D
B
CPLD - INPUT
DIR Register
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
MUX
PORT Pin
DATA OUT
AI04936B



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