PSD4235G2V-10UI datasheet(63/100 Pages) STMICROELECTRONICS

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PSD4256G6V

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

JTAG In-System Programming (ISP)

Port E is JTAG compliant, and can be used for In-

System Programming (ISP). You can multiplex

JTAG operations with other functions on Port E

because In-System Programming (ISP) is not per-

formed during normal system operation. For more

information on the JTAG Port, see the section en-

titled “RESET”, on page 34.

MCU RESET Mode

Ports F and G can be configured to operate in

MCU RESET Mode. This mode is available when

PSD is configured for the Motorola 16-bit 683xx

and HC16 family and is active only during reset.

At the rising edge of the RESET input, the MCU

reads the logic level on the data bus (D15-D0)

pins. The MCU then configures some of its I/O pin

functions according to the logic level input on the

data bus lines. Two dedicated buffers are usually

enabled during RESET to drive the data bus lines

to the desired logic level.

The PSD can replace the two buffers by configur-

ing Ports F and G to operate in MCU RESET

Mode. In this mode, the PSD will drive the pre-de-

fined logic level or data pattern on to the MCU data

bus when RESET is active and there is no ongoing

bus cycle. After RESET, Ports F and G return to

the normal Data Port mode.

The MCU RESET Mode is enabled and configured

in PSDsoft. The user defines the logic level (data

pattern) that will be drive out from Ports F and G

during RESET.

Port Configuration Registers (PCR)

Each Port has a set of Port Configuration Regis-

ters (PCR) used for configuration. The contents of

the registers can be accessed by the MCU through

normal READ/WRITE bus cycles at the addresses

given in Table 6, page 19. The addresses in Table

6 are the offsets in hexadecimal from the base of

the CSIOP register.

The pins of a port are individually configurable and

each bit in the register controls its respective pin.

For example, bit 0 in a register refers to bit 0 of its

port. The three Port Configuration Registers

(PCR), shown in Table 42, are used for setting the

Port configurations. The default Power-up state for

each register in Table 42 is 00h.

Control Register

Any bit reset to '0' in the Control Register sets the

corresponding port pin to MCU I/O mode, and a 1

sets it to Address Out mode. The default mode is

MCU I/O. Only Ports E, F and G have an associat-

ed Control Register.

Table 42. Port Configuration Registers (PCR)

Note: 1. See Table 46, page 64 for Drive Register bit definition.

Port

MCU Access

Control

E, F, G

WRITE/READ

Direction

A, B, C, D, E, F, G

WRITE/READ

Drive Select1

A, B, D, E, G

WRITE/READ

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