ADPD6000 datasheet(25/89 Pages) AD

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Data Sheet

ADPD6000

THEORY OF OPERATION

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FIFO_TH register. The INT_FIFO_TH bit is cleared automatically

when a FIFO read reduces the number of bytes below the value in

the FIFO_TH register, which allows the user to set an appropriate

data size for their host needs.

The INT_FIFO_TH bit does not trigger if the FIFO byte count

exceeds the threshold in the middle of any write of complete data.

Instead, the INT_FIFO_TH bit is set at the next write to the FIFO.

For example, if only PPG TSA is running, it only writes 4-byte lit

data to the FIFO. Figure 37 shows the data in the FIFO.

Figure 37. FIFO Threshold Interrupt Example

If the threshold is set as 4, the interrupt triggers at the beginning of

the second TSA data write to the FIFO. If the threshold is set as 5,

6, or 7, the INT_FIFO_TH bit does not trigger until the write of the

third TSA data. This method can help prevent any partial data read

from the FIFO.

Clearing Interrupt Status Bits

All status bits are set regardless of whether the status bit is routed

to one of the interrupt outputs, Interrupt X or Interrupt Y. The status

bits are independent of the interrupt enable bits. The status bits are

always set by the corresponding event. The interrupt bits stay set

until they are either manually or automatically cleared.

The user can manually clear a given interrupt by writing a 1 to

the matching interrupt status bit. In addition, the data interrupt

status bits can be configured to clear automatically. When the

INT_ACLEAR_FIFO bit is set, the appropriate interrupt status bit

is automatically cleared when any matching FIFO register is read.

Automatic clearing of the interrupt status bits removes the need to

manually clear these interrupts.

Optional Status Bytes

There is an option to append each data packet with status bits. This

option is useful for hosts that cannot spare an interrupt channel

to service. The status bytes can each be individually selected

in the FIFO_STATUS_BYTES register. Each bit in the FIFO_ STA-

TUS_BYTES register enables a status byte that is appended to the

data packet in the FIFO. If any bit in the FIFO_STATUS_ BYTES

contains the status bits.

The 4-bit sequence number cycles from 0 to 15 and is incremented

with a wraparound every time the time slot sequence completes.

This sequence number can also be made available bitwise on the

GPIOx pins.

Interrupt Outputs, Interrupt X and Interrupt Y

The ADPD6000 supports two separate interrupt outputs, Interrupt X

and Interrupt Y. Each interrupt has the option to be driven to any

of the four GPIOx pins. The two different interrupt outputs can be

generated for a host processor if desired. For example, the FIFO

threshold interrupt, INT_FIFO_TH, can be routed to Interrupt X and

used to drive the direct memory access (DMA) channel of the host,

while the INT_FIFO_OFLOW and INT_FIFO_UFLOW interrupts

can be routed to Interrupt Y and used to drive an additional host

interrupt pin.

For each interrupt, there is an associated Interrupt X and Interrupt

Y enable bit. See Table 1 for a full list of available interrupts that

can be brought out on Interrupt X and Interrupt Y. The logic for the

Interrupt X and Interrupt Y function is a logic AND of the status

bit with its matching enable bit. All enabled status bits are then

logically OR’ed to create the interrupt function. The enable bits do

not affect the status bits.

General-Purpose I/Os

The ADPD6000 provides three general-purpose I/O pins: GPIO0,

GPIO1, and GPIO2. These GPIOs can be used as previously

described in the Interrupt Outputs, Interrupt X and Interrupt Y

section for interrupt outputs or for providing external clock signals to

the device. The GPIOs can also be used for many different control

signals, as synchronization controls to external devices, as well as

test signals that are useful during system debugging. All of the

available signals that can be brought out on a GPIOx pin are listed

in Table 1.

IOVDD Supply Voltage Consideration

The ADPD6000 can operate with IOVDD as low as 1.7 V and as

high as 3.6 V. LOW_IOVDD_EN in Register 0x0057 is set to 0x1 for

IOVDD lower than 3 V. 0x1 is the default value for this bit because

the typical IOVDD value is 1.8 V.

If 3 V or higher is supplied for IOVDD, the LOW_IOVDD_EN bit

must be set to 0x0 for proper operation.

SPI

The ADPD6000 contains an SPI port that operates synchronously

with its input clocks.

The ADPD6000 has an internal power-on reset circuit that sets the

device into a known idle state during the initial power-up. After the

power-on reset is released, approximately 2 µs to 6 μs after the

DVDD supply is active, there is an initialization state that sets the

15 µs to 20 µs. The device can then be read and written through

the SPI.

The registers are accessed using addresses within a 15-bit address

space. Each address references a 15-bit register with one address

reserved for the FIFO read accesses. For SPIs, reads and writes

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