ADPD6000 datasheet(18/89 Pages) AD

18 / 89 page

Data Sheet

ADPD6000

THEORY OF OPERATION

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Rev. 0 | 18 of 89

PPG channel can start normal operation–for example, if in digital

integration mode, the PPG receiver channel can start to take dark

samples. This ambient baseline is used in the time slot if coarse

tuning only mode is enabled.

If coarse and fine tuning loop mode is enabled, the coarse tuning

circuit works the same way as in coarse tuning mode. However, the

ambient DAC code updates after each dark sample measurement.

Select these two modes with the AMBIENT_CANCELLATION_x

bits for system level design flexibility.

Coarse loop mode makes the measurement to find the accurate

value of the ambient current. Then, the ambient DAC subtracts the

ambient current at the beginning of the signal chain so that it does

not corrupt the PPG signal measurement.

Both analog integration mode and digital integration mode can

perform coarse loop ambient rejection.

The fine tuning loop updates the ambient information after each

dark sample measurement. This feature is available only in digital

integration mode.

The MCU mode allows the user to subtract the ambient current.

The DAC_AMBIENT_CH1_x and DAC_AMBIENT_CH2_x bits are

designed to allow the user to fill in the current ambient value, and

the AFE then subtracts that value from the signal chain. DAC_AM-

BIENT_CH1_x and DAC_AMBIENT_CH2_x are 9-bit fields, with

each LSB representing a 0.6 μA step in a 0 μA to 300 μA range.

LED DC Cancellation

Besides the ambient DAC, there is another IDAC at the input of

each signal chain. This IDAC is used to subtract the unwanted dc

component in the reflected LED to increase the dynamic range of

the receiver channel.

These two IDACs are controlled by the MCU only. The

DAC_LED_DC_CH1_x and DAC_LED_DC_CH2_x bits control the

LED dc canceling, 7-bit IDAC with full scale.

The LED dc subtraction feature is available only for digital integra-

tion mode.

A certain amount of dc current can be subtracted from the

AFE based on the top level optical and system design.

DAC_LED_DC_CH1_x and DAC_LED_DC_CH2_x are 7-bit fields,

with each LSB representing a 1.5 μA step in a 0 μA to 190 μA

range.

LED Drivers

The optical path has two LED drivers, each of which is brought

out to two LED driver outputs, providing a total of four LED output

drivers. The device can drive up to two LEDs simultaneously, one

from each driver pair. The LED output driver is a current sink.

Figure 28 shows an example of a single LED driver output pair.

Figure 28. LED Driver Output Pair

The LED driver output pins (LED1A, LED1B, LED2A, and LED2B)

have a maximum allowable pin voltage of 3.6 V. Any voltage expo-

sure over this rating affects the reliability of the device operation

and, in certain circumstances, causes the device to cease proper

operation. The voltage of the LED driver output pins must not be

confused with the supply voltages of the LEDs. VLEDx is the voltage

applied to the anode of the external LED, whereas the LED output

driver pin is connected to the cathode of the external LED. The

compliance voltage is the amount of headroom voltage at the LED

driver pin, measured with respect to ground, required to maintain

the programmed LED current level. The compliance voltage is a

function of the current required.

ECG SIGNAL CHAIN

The ECG channel measures the differential voltage across two

electrodes to create a lead measurement. The output of this chan-

nel is a 24-bit digital word representing the measured ECG voltage.

The maximum input differential signal is ±1.2 V, and the LSB size is

286 nV. The output data rate can be 250 SPS, 500 SPS, 1 kSPS, 2

kSPS, or 4 kSPS. This filter selection affects the digital processing

but not the analog processing. Additionally, a 4 kHz ac lead off

signal is converted by the analog ECG path and extracted in the

digital domain.

The ECG channel has a dedicated ADC path with feedback ar-

rangement to remove the dc offset presented by the ECG electro-

des. The ECG channel is designed to provide a high quality ECG

signal process while suppressing the large dc offset that is caused

by the complex system design.

Both DCLO detection and ACLO detection are integrated to accom-

modate different complex lead contact conditions to provide reliable

lead information.

The RLD pin is designed to better bias the human body potential to

avoid interference.

ECGIP and ECGIN are the signal inputs for the ECG channel, and

they must be connected to the input leads. The RLD pin must be

connected to the reference lead.

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