ADPD6000 datasheet(35/89 Pages) AD

35 / 89 page

Data Sheet

ADPD6000

APPLICATIONS INFORMATION

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Rev. 0 | 35 of 89

02E1 99A2 #sinewave frequency is 50kHz

02EB 5610 #switch connection to measure exter►

nal Rdut voltage

02ED 0004 #bypass the SINC filter

02EE 0008 #DFT number is 1024

# BIOZ Time slot D configure #

0300 0003 #tia/dacref enable

0307 320D #exbuf enable

030A 2E30 #amp/pag enable

0302 0001 #sinewave frequency is 50kHz

0301 99A2 #sinewave frequency is 50kHz

030B 4210 #switch connection to measure exter►

nal Rdut current

030D 0004 #bypass the SINC filter

030E 0008 #DFT number is 1024

0010 C201 # enable BIOZ timeslot ABCD, PPG

timeslot AB and ECG, go

## Interrupt mapping of fifo_th

0014 8000 # FIFO_th to INX

0022 0003 # GPIO0 output invert

0023 0002 # gpio0 int x

0010 C201 # operation mode set to GO

Power-Up Sequencing

Note that the power supplies need to be on and off simultaneously.

FIFO Data Structure

Table 19 shows the data structure in the FIFO for the recommended

multimodal measurement configuration. There are 52 bytes for

every data pattern.

Table 19. Data Structure in FIFO

Byte Order in FIFO

Description

Byte 0 to Byte 19

ECG data: 20 bytes

Byte 20 to Byte 23

PPG_A data: 4 bytes

Byte 24 to Byte 27

PPG_B data: 4 bytes

Byte 28 to Byte 33

BIOZ_A data: 6 bytes

Byte 34 to Byte 39

BIOZ_B data: 6 bytes

Byte 40 to Byte 45

BIOZ_C data: 6 bytes

Byte 46 to Byte 51

BIOZ_D data: 6 bytes

DESIGN GUIDE

The ADPD6000 is a multimodal, vital sign monitoring AFE. The

performance of the device can be adversely impacted by the PCB

layout, especially for the analog input interfaces.

Power Rails

For the power supply, decouple the AVDD, AVDD3, DVDD, and

IOVDD pins with a 0.1 μF or larger ceramic chip capacitor to the

PCB ground plane placed near the power pins. It is recommended

that all decoupling capacitors use individual vias to the PCB ground

plane to avoid mutual impedance coupling between decoupled

supplies when sharing vias.

Optical Channel

For the PPG channel, decouple the VREF1 pin and VREF2 pin to

the PCB ground plane with a 1.0 μF ceramic capacitor. The voltage

on the VREF1 pin and VREF2 pin is nominally 1.2 V. Therefore,

a 6.3 V rated ceramic capacitor is adequate for this purpose. The

most critical aspect of the PCB layout of the ADPD6000 is the

handling of the IN1, IN2, IN3, and IN4 nodes. Because photodiode

input is sensitive to noise, and any parasitic capacitive coupling to

the pin can result in additional noise, it is recommended that the

photodiode input trace in the layout be as short as possible and

fully guarded by the ground plane.

For example, as a 6-layer stack design, the chip is placed in the top

layer with optical components in the bottom layer. Therefore, it is

recommended that the IN1, IN2, IN3, and IN4 trace length in the top

is short to avoid parasitic effects. In the bottom layer, the IN1, IN2,

IN3, and IN4 traces and the photodiode anode are fully guarded

with the ground shape and trace. VC1, VC2, and the photodiode

cathode are also guarded with the ground plane. Layer 5 is filled

with a ground plane for reference. Keep the analog input signals

away from other digital or noisy signals.

ECG Channel

For the ECG channel, both traces of ECGIP and ECGIN must

match to achieve high CMRR performance. Use a differential pair

layout for ECGIP and ECGIN and shorten the length of the traces.

BIA Channel

For the BIA channel, minimize the length of the PCB trace for

RCALP and RCALN because the RCALP and RCALN value is

critical for the BIOZ measurement accuracy. The resistance of

the PCB trace is designed to guarantee that the accuracy of the

RCALP and RCALN resistance is 0.1%, even including the PCB

wire resistance.

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