ADPD6000 datasheet(24/89 Pages) AD

24 / 89 page

Data Sheet

ADPD6000

THEORY OF OPERATION

analog.com

Rev. 0 | 24 of 89

If using a dedicated pin for a time stamp that does not have

transitions other than the time stamp, set the TIMESTAMP_ AL-

WAYS_EN bit to avoid automatic clearing of the CAPTURE_ TIME-

STAMP bit. This setting removes the need to enable the time stamp

capture each time.

The host can also use TIMESTAMP_SLOT_DELTA to determine

when the next time slot occurs. TIMESTAMP_SLOT_DELTA can

determine the arrival time of the samples currently in the FIFO.

The time stamp trigger is edge sensitive and can be set to

either trigger on the rising edge (default) or falling edge using

TIMESTAMP_INV.

Low Frequency Oscillator Calibration

The time stamp circuitry can calibrate the 960 kHz low fre-

quency oscillator circuit by adjusting the frequency to match

the timing of the time stamp triggers. Simply compare the

TIMESTAMP_COUNT_x value in low frequency oscillator cy-

cles to the actual time stamp trigger period and adjust the

OSC_960K_FREQ_ADJ value accordingly.

High Frequency Oscillator Calibration

The high frequency oscillator is calibrated by comparing multiples of

its cycles with multiple cycles of the low frequency oscillator, which

is calibrated to the system time. Calibration of the low frequency

oscillator precedes calibration of the high frequency oscillator. The

method for calibrating the high frequency oscillator is as follows:

1. Set OSC_CAL_ENABLE = 1 to enable the oscillator calibration

circuitry.

2. Write 1 to the OSC_32M_CAL_START bit.

3. The ADPD6000 automatically powers up the high frequency

oscillator.

4. The device automatically waits for the high frequency oscillator

to be stable.

5. An internal counter automatically counts the number of 32 MHz

high frequency oscillations that occur during 128 cycles of the

960 kHz low frequency oscillator.

6. The OSC_32M_CAL_COUNT bits update with the final count.

7. The 32 MHz oscillator automatically powers down following

calibration unless time slots are active.

8. The device resets the OSC_32M_CAL_START bit indicating the

count has updated.

The OSC_32M_FREQ_ADJ bits adjust the frequency of the 32

MHz oscillator to the desired frequency. When using an external

low frequency oscillator, the 32 MHz oscillator calibration is per-

formed with respect to the externally provided low frequency oscilla-

tor.

When the calibrations of the low frequency and high frequency

oscillators are complete, set CLK_CAL_ENA = 0 to disable the

clocking of the oscillator calibration circuitry to reduce the power

consumption. CLK_CAL_ENA defaults to 0 so that the calibration

circuitry is disabled by default.

EXECUTION MODES

A state machine in the low frequency oscillator clock domain

controls sleep times, wake-up cycles, and the start of time slot

operations. The low frequency oscillator serves as the time base

for all time slot operations, controls the sample rates, and clocks

the low frequency state machine. This state machine controls all

operations and is controlled by the OP_MODE bit.

Table 12. OP_MODE Bit Setting Descriptions

OP_MODE Setting Mode

Description

Standby

All operations stopped. Time slot actions reset.

Low power standby state.

Transitioning to this state from standby mode

starts time slot operation.

At power-up and following any subsequent reset operations, the

ADPD6000 is in standby mode. The user can write 0 to the

OP_MODE bit to immediately stop operations and return to standby

mode.

The time slots are enabled by the ECG_TIMESLOT_EN,

PPG_TIMESLOT_EN, and BIOZ_TIMESLOT_EN bits in the OP-

MODE register (see Table 1). Set ECG_TIMESLOT_EN to 1 ena-

ble the ECG time slot. Set the BIOZ_TIMESLOT_EN value and

PPG_TIMESLOT_EN value to enable the corresponding BIOZ time

slots and PPG time slots, respectively.

After enabling the desired time slots, set the OP_MODE bit to 1 to

start the chip operation.

go mode. The user must enter standby mode before changing the

control registers. Standby mode resets the digital portion of the

ADC, all of the pulse generators, and the state machine.

When OP_MODE is set to 1, the device immediately starts the first

wake-up sequence and time slot operations unless using an exter-

nal synchronization trigger. If using an external synchronization

trigger, the device enters the sleep state before the first wake-up

and time slot regions begin.

HOST INTERFACE

The ADPD6000 uses an SPI to communicate with other devices.

The device also provides numerous FIFO, error, and threshold

status bits, each of which can be provided by an interrupt function

from a GPIO, read from status registers, or appended as optional

status bytes at the end of a FIFO packet.

Interrupt Status Bits

FIFO Threshold Interrupt

The FIFO threshold interrupt status bit, INT_FIFO_TH, is set when

the number of bytes in the FIFO exceeds the value stored in the

ADPD6000 датащи(PDF) 24 Page - Analog Devices

ADPD6000 датащи(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

датащи скачать

ссылки URL