ADPD6000 datasheet(65/89 Pages) AD

65 / 89 page

Data Sheet

ADPD6000

analog.com

Rev. 0 | 65 of 89

Table 21. Register Details

Reg

Name

Bits

Bit Name

Description

Reset Access

0x0000 FIFO_STATUS

CLEAR_FIFO

Clear FIFO. Write a 1 to empty the FIFO while not oper-

ating. This resets FIFO_BYTE_COUNT and also clears the

INT_FIFO_OFLOW, INT_FIFO_UFLOW, and INT_FIFO_TH sta-

tus bits. After the FIFO is cleared, CLEAR_FIFO must be set to

0 for the FIFO function.

0x0

R0/W

INT_FIFO_UFLOW

FIFO underflow error. This bit is set when the FIFO is read while

empty. Write 1 to this bit to clear the interrupt. This bit is also

cleared if the FIFO is cleared using the CLEAR_FIFO bit.

0x0

R/W1C

INT_FIFO_OFLOW

FIFO overflow error. This bit is set when data is not written to

the FIFO due to a lack of space. Write 1 to this bit to clear the

interrupt. This bit is also cleared if the FIFO is cleared with the

CLEAR_FIFO bit.

0x0

R/W1C

INT_FIFO_TH

FIFO_TH interrupt status. This bit is set during a FIFO write

when the number of bytes in the FIFO exceed the FIFO_TH

can also be automatically cleared when the FIFO data register is

read if the INT_ACLEAR_FIFO bit is set.

0x0

R/W1C

FIFO_INIT_DONE_STATUS

FIFO initialization process is finished. Note that this bit is a

status bit and is not sent to the interrupt. This bit is set after the

FIFO self initialization process.

0x0

[10:0]

FIFO_BYTE_COUNT

Number of bytes in FIFO. This field indicates the number of

bytes in the FIFO.

0x0

0x0004 ECG_STATUS

[15:8]

RESERVED

Reserved.

0x0

ECG_ACLO_STATUS

ECG ACLO status bit. Write 1 to this bit to clear this status.

0x1

R/W1C

ECGIN_DCLO_HI_STATUS

ECGIN DCLO HI status bit. Write 1 to this bit to clear this status. 0x1

R/W1C

ECGIP_DCLO_HI_STATUS

ECGIP DCLO HI status bit. Write 1 to this bit to clear this status. 0x1

R/W1C

ECG_RLD_DCLO_HI_STATUS

ECG RLD DCLO HI status bit. Write 1 to this bit to clear this

status.

0x1

R/W1C

ECG_RLD_DCLO_LO_STATUS

ECG RLD DCLO LO status bit. Write 1 to this bit to clear this

status.

0x1

R/W1C

ECG_DCLO_STATUS

ECG DCLO status bit. Write 1 to this bit to clear this status.

0x1

R/W1C

ECG_PGA_SAT_STATUS

ECG PGA saturation status bit. Write 1 to this bit to clear this

status.

0x0

R/W1C

ECG_ADC_SAT_STATUS

ECG ADC saturation status bit. Write 1 to this bit to clear this

status.

0x0

R/W1C

0x0005 GLOBAL_STATUS

[15:1]

RESERVED

Reserved.

0x0

INVALID_CFG_STATUS

Status bit indicating that TIMESLOT_PERIOD_x is not

configured properly. Write 1 to this bit to clear this status.

0x0

R/W1C

0x0006 FIFO_TH

[15:10]

RESERVED

Reserved.

0x0

[9:0]

FIFO_TH

FIFO interrupt generation threshold. This bit generates the FIFO

interrupt during a FIFO write when the number of bytes in the

FIFO exceeds this value.

0x0

R/W

0x0007 INT_ACLEAR

INT_ACLEAR_FIFO

FIFO threshold interrupt automatic clear enable. Set this bit to

enable automatic clearing of the FIFO_TH bit interrupt each time

the FIFO is read.

0x1

R/W

[14:0]

RESERVED

Reserved.

0x0

0x0008 CHIP_ID

[15:8]

RESERVED

Reserved.

0x0

[7:0]

CHIP_ID

Chip ID.

0xC4

0x0009 OSC32M

[15:8]

RESERVED

Reserved.

0x0

[7:0]

OSC_32M_FREQ_ADJ

High frequency oscillator frequency control. 0x00 is the lowest

frequency, and 0xFF is maximum frequency.

0x80

R/W

ADPD6000 датащи(PDF) 65 Page - Analog Devices

ADPD6000 датащи(HTML) 65 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

датащи скачать

ссылки URL