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ADPD6000 датащи(PDF) 76 Page - Analog Devices |
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ADPD6000 датащи(HTML) 76 Page - Analog Devices |
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76 / 89 page ![]() Data Sheet ADPD6000 REGISTER DETAILS analog.com Rev. 0 | 76 of 89 Table 21. Register Details Reg Name Bits Bit Name Description Reset Access 0100: IN2 connected to Channel 2. IN1 disconnected. 0101: IN1 connected to Channel 1. IN2 connected to Channel 2. 0110: IN2 connected to Channel 1. IN1 connected to Channel 2. 0111: IN1 and IN2 connected to Channel 1. Single-ended or differential, based on PAIR12. 1000: IN1 and IN2 connected to Channel 2. Single-ended or differential, based on PAIR12. 0x0123 CATHODE_A 15 RESERVED Reserved. 0x0 R 0x0143 CATHODE_B [14:12] PRECON_x Precondition value for enabled inputs during this time slot. 0x0 R/W 0x0163 CATHODE_C 000: float inputs. 0x0183 CATHODE_D 001: precondition to VC1. 0x01A3 CATHODE_E 010: precondition to VC2. 0x01C3 CATHODE_F 011: precondition to VICM. 0x01E3 CATHODE_G 100: precondition with TIA input. 0x0203 CATHODE_H 101: precondition with TIA_VREF. 0x0223 CATHODE_I 110: Precondition by shorting differential pair. 0x0243 CATHODE_J [11:10] VC2_PULSE_x VC2 pulse control. 0x0 R/W 0x0263 CATHODE_K 00: no pulsing. 0x0283 CATHODE_L 01: alternate odd/even time slots. 10: pulse to alternate value using modulate pulse. 11: leave VC2 floating. [9:8] VC2_ALT_x VC2 alternate pulsed state for this time slot. 0x0 R/W 00: AVDD. 01: TIA_VREF. 10: TIA_VREF + 215 mV (V_DELTA). 11: GND. [7:6] VC2_SEL_x VC2 active state for this time slot. 0x0 R/W 00: AVDD. 01: TIA_VREF. 10: V_DELTA. 11: GND. [5:4] VC1_PULSE_x VC1 pulse control. 0x0 R/W 00: no pulsing. 01: alternate odd/even times lots. 10: pulse to alternate value using modulate pulse. 11: leave VC1 floating. [3:2] VC1_ALT_x VC1 alternate pulsed state for Time Slot x. 0x0 R/W 00: AVDD. 01: TIA_VREF. 10: V_DELTA. 11: GND. [1:0] VC1_SEL_x VC1 active state for Time Slot x. 0x0 R/W 00: AVDD. 01: TIA_VREF. 10: V_DELTA. 11: GND. 0x0124 AFE_TRIM1_A 15 TIA_CEIL_DETECT_EN_x Enable TIA saturation detection. Set to 1 to enable TIA saturation detection circuitry. Enables Channel 1 and also Channel 2 if Channel 2 is enabled. 0x0 R/W |
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