ADC3641 datasheet(26/77 Pages) TI

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8.3.2 Clock Input

In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential

signaling with a high slew rate. This is especially important in IF sampling applications. For less jitter sensitive

applications, the ADC364x provides the option to operate with single ended signaling which saves additional

power consumption.

8.3.2.1 Single Ended vs Differential Clock Input

The ADC364x can be operated using a differential or a single ended clock input where the single ended clock

consumes less power consumption. However clock amplitude impacts the ADC aperture jitter and consequently

the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to be provided.

• Differential Clock Input: The clock input can be AC coupled externally. The ADC364x provides internal biasing

for that use case.

• Single Ended Clock Input: This mode needs to be configured using SPI register TBD. In this mode there is no

internal clock biasing and thus the clock input needs to be DC coupled around a 0.9V center. The unused

input needs to be AC coupled to ground.

VCM

0.9V

CLKP

CLKM

5kO

CLKP

CLKM

0.9V

1.8V

Figure 8-13. External and internal connection using differential (left) and single ended (right) clock input

8.3.2.2 Signal Acquisition Time Adjust

The ADC364x includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for

clock rates below 40 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer

time for the driving amplifier to settle out the signal which can improve the SNR performance of the system.

Note

This register needs to be set for the 65 MSPS speed grade (ADC3643) when operating at sampling

rates below 40 MSPS. For the 10 and 25 MSPS device speed grades the sampling time is already set

to TS/2.

When powering down the DLL, the acquisition time tracks the clock duty cycle (50% is recommended).

Table 8-1. Acquisition time vs DLL PDN setting

SAMPLING CLOCK FS (MSPS)

DLL PDN (0x11, D2)

ACQUISITION TIME (tACQ)

TS / 4

≤ 40

TS / 2

TS: Sampling clock period

ADC3643

SBAS886 – OCTOBER 2020

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