ADC3641 datasheet(40/77 Pages) TI

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8.3.5.5 Output Interface/Mode Configuration

The following sequence summarizes all the relevant registers for changing the output interface and/or enabling

the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining

steps can come in any order.

Table 8-9. Configuration steps for changing interface or decimation

STEP

FEATURE

ADDRESS

DESCRIPTION

Output Interface

0x07

Select the output interface bit mapping depending on resolution and output interface.

Output Resolution

DDR

2-wire

1-wire

1/2-wire

14-bit

0xA9

0x2B

0x6C

0x8D

16-bit

0x4B

18-bit

N/A

0x2B

20-bit

N/A

0x4B

0x13

Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to 0x01, wait

~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00

0x0A/B/C

When changing the output interface bit mapper (0x07), the CMOS output buffer register has to be configured

again.

0x18

For serial CMOS modes, DCLKIN EN (D4) needs to be enabled.

0x19

In serial CMOS, configure the FCLK registers based on bypass/decimation and # of lanes used.

Bypass/Decimation

SCMOS

FCLK SRC

(D7)

FCLK DIV

(D4)

TOG FCLK

(D0)

Bypass/ Real Decimation

2-wire

1-wire

1/2-wire

Complex Decimation

2-wire

1-wire

1/2-wire

0x1B

Select the output interface resolution using the bit mapper (D5-D3).

0x1F

For serial CMOS modes, DCLKIN EN (D6) and DCLK OB EN (D4) need to be enabled.

0x20

0x21

0x22

In serial CMOS, select the FCLK pattern for decimation for proper duty cycle output of the FCLK.

Decimation

Output

Resolution

2-wire

1-wire

1/2-wire

Real Decimation

14-bit

use default

0xFE000

use default

16-bit

0xFF000

18-bit

0xFF800

20-bit

0xFFC00

Complex Decimation

14-bit

0xFFFFF

16-bit

18-bit

20-bit

Decimation Filter

0x24

Enable the decimation filter

0x25

Configure the decimation filter

0x2A/B/C/D

0x31/2/3/4

Program the NCO frequency for complex decimation (can be skipped for real decimation)

0x27

0x2E

Configure the complex output data stream (set both bits to 0 for real decimation)

Serial CMOS

OP-Order (D4)

Q-Delay (D3)

2-wire

1-wire

1/2-wire

0x26

Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.

ADC3643

SBAS886 – OCTOBER 2020

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