ADC3641 datasheet(21/77 Pages) TI

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8 Detailed Description

8.1 Overview

The ADC364x is a low noise, ultra-low power 14-bit high-speed dual channel ADC family supporting sampling

rates from 10 to 65 Msps. It offers very good DC precision together with IF sampling support which makes it

ideally suited for a wide range of applications. The ADC364x is equipped with an on-chip internal reference

option but it also supports the use of an external, high precision 1.6 V voltage reference or an external 1.2 V

reference which is buffered and gained up internally. Because of the inherent low latency architecture, the digital

output result is available after only one clock cycle. Single ended as well as differential input signaling is

supported.

An optional programmable digital down converter enables external anti-alias filter relaxation as well as output

data rate reduction. The digital filter provides a 32-bit programmable NCO and supports both real or complex

decimation.

The ADC364x family uses a parallel DDR CMOS as well as a 2-wire, 1-wire and 1/2-wire serial CMOS interface

to output the data offering lowest power digital interface together with the flexibility to minimize the number of

digital interconnects. The ADC364x includes a digital output formatter which supports output resolutions from 14

to 20-bit. The device is a pin-to-pin compatible family with different speed grades.

The device features and control options can be set up either through pin configurations or via SPI register writes.

8.2 Functional Block Diagram

Control

AIN

CLK

VREF

ADC

14 bit

1.2 V REF

REFBUF

Digital Downconverter

NCO

BIN

ADC

14 bit

NCO

0.95 V

VCM

DB0..6

DCLK

DA0..6

Dig I/F

CMOS

Crosspoint

Switch

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ADC3643

SBAS886 – OCTOBER 2020

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