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8.3.5.5.1 Configuration Example

The following is a step by step programming example to configure the ADC364x to complex decimation by 8 with

1-wire serial CMOS and 16-bit output.

1. 0x07 (address) 0x6C (load bit mapper configuration for 16-bit output with 1-wire serial CMOS)

2. 0x13 0x01, wait 1 ms, 0x13 0x00 (load e-fuse)

3. 0x0A 0xFF, 0x0B 0xEE, 0x0C 0xFD (Power down unused CMOS output buffers to avoid contention)

4. 0x18 0x10 (DCLKIN EN for serial CMOS mode)

5. 0x19 0x82 (configure FCLK)

6. 0x1B 0x88 (select 16-bit output resolution)

7. 0x1F 0x50 (DCLKIN EN for serial CMOS mode)

8. 0x20 0xFF, 0x21 0xFF, 0x22 0x0F (configure FCLK pattern)

9. 0x24 0x06 (enable decimation filter)

10.0x25 0x30 (configure complex decimation by 8)

11.0x2A/B/C/D and 0x31/32/33/34 (program NCO frequency)

12.0x27/0x2E 0x08 (configure Q-delay register bit)

13.0x26 0xAA, 0x26 0x88 (set digital mixer gain to 6-dB and toggle the mixer update)

8.3.6 Test Pattern

In order to enable in-circuit testing of the digital interface, the following test patterns are supported and enabled

via SPI register writes (0x14/0x15/0x16). In decimation mode (real and complex), the test patterns replace the

output data of the DDC - however channel A controls the test patterns for both channels.

• RAMP Pattern: The step size needs to be configured in the CUSTOM PAT register according to the native

resolution of the ADC. When selecting a higher output resolution then the additional LSBs will still be 0 in

RAMP pattern mode.

– 00001: 18-bit output resolution

– 00100: 16-bit output resolution

– 10000: 14-bit output resolution

• Custom Pattern: Configured in the CUSTOM PAT register

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ADC3643

SBAS886 – OCTOBER 2020

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ADC3641 датащи(PDF) 41 Page - Texas Instruments