ADC3641 datasheet(13/77 Pages) TI

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6.10 Timing Requirements (continued)

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to T

MAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

INTERFACE TIMING - SERIAL CMOS

tPD

Propagation delay: sampling clock falling

edge to DCLK rising edge

Delay between sampling clock falling edge to

DCLKIN falling edge < 2.5ns.

TDCLK = DCLK period

tCDCLK = Sampling clock falling edge to

DCLKIN falling edge

2 + T

DCLK +

tCDCLK

3 + T

DCLK +

tCDCLK

4 + T

DCLK +

tCDCLK

Delay between sampling clock falling edge to

DCLKIN falling edge >= 2.5ns.

TDCLK = DCLK period

tCDCLK = Sampling clock falling edge to

DCLKIN falling edge

2 + t

CDCLK

3 + t

CDCLK

4 + t

CDCLK

tCD

DCLK rising edge to output data delay,

2-wire serial CMOS

Fout = 10 MSPS, DA/B5,6 = 80 MBPS

-0.24

0.10

Fout = 20 MSPS, DA/B5,6 = 160 MBPS

-0.29

0.10

Fout = 30 MSPS, DA/B5,6 = 240 MBPS

-0.28

0.09

DCLK rising edge to output data delay,

1-wire series CMOS

Fout = 5 MSPS, DA/B6 = 80 MBPS

-0.22

0.11

Fout = 10 MSPS, DA/B6 = 160 MBPS

-0.27

0.11

Fout = 15 MSPS, DA/B6 = 240 MBPS

-0.52

0.08

DCLK rising edge to output data delay, 1/2-

wire serial CMOS

Fout = 5 MSPS, DA6 = 160 MBPS

-0.24

0.10

tDV

Data valid, 2-wire serial CMOS

Fout = 10 MSPS, DA/B5,6 = 80 MBPS

12.19 12.36

Fout = 20 MSPS, DA/B5,6 = 160 MBPS

5.93

6.1

Fout = 30 MSPS, DA/B5,6 = 240 MBPS

3.91

4.07

Data valid, 1-wire serial CMOS

Fout = 5 MSPS, DA/B6 = 80 MBPS

12.21 12.39

Fout = 10 MSPS, DA/B6 = 160 MBPS

5.95

6.1

Fout = 15 MSPS, DA/B6 = 240 MBPS

3.83

4.08

Data valid, 1/2-wire serial CMOS

Fout = 5 MSPS, DA6 = 160 MBPS

5.36

6.13

SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input

fCLK(SCLK) Serial clock frequency

MHz

tSU(SEN)

SEN to rising edge of SCLK

tH(SEN)

SEN from rising edge of SCLK

tSU(SDIO)

SDIO to rising edge of SCLK

tH(SDIO)

SDIO from rising edge of SCLK

SERIAL PROGRAMMING INTERFACE (SDIO) - Output

t(OZD)

SDIO tri-state to driven

3.9

10.8

t(ODZ)

SDIO data to tri-state

3.4

t(OD)

SDIO valid from falling edge of SCLK

3.9

10.8

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ADC3643

SBAS886 – OCTOBER 2020

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