ADC3641 datasheet(62/77 Pages) TI

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When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into

consideration. For example, the ADC364x input full-scale is 2.25 Vpp. When factoring in ~ 1 dB for insertion loss

of the filter, then the amplifier needs to deliver close to 2.5 Vpp. The amplifier distortion performance will degrade

with a larger output swing and considering the ADC common mode input voltage the amplifier may not be able to

deliver the full swing. The ADC364x provides an output common mode voltage of 0.95V and the THS4541 for

example can only swing within 250 mV of its negative supply. A unipolar 3.3 V amplifier power supply will thus

limit the maximum voltage swing to ~ 2.8Vpp. Additionally input voltage protection diodes may be needed to

protect the ADC from over-voltage events.

Table 9-2. Output voltage swing of THS4541 vs power supply

DEVICE

MIN OUTPUT VOLTAGE

MAX SWING WITH 3.3 V/ 0 V SUPPLY

THS4541

VS- + 250 mV

2.8 Vpp

9.1.2 Detailed Design Procedure

9.1.2.1 Input Signal Path

Depending on desired input signal frequency range the THS4551 and THS4541 provide very good low power

options to drive the ADC inputs. Table 9-3 provides a comparison between the THS4551 and THS4541 and the

power consumption vs usable frequency trade off.

Table 9-3. Fully Differential Amplifier Options

DEVICE

CURRENT (IQ) PER CHANNEL

USABLE FREQUENCY RANGE

THS4561

0.8 mA

< 3 MHz

THS4551

1.4 mA

< 10 MHz

THS4541

10 mA

< 70 MHz

The low pass filter design (topology, filter order) is driven by the application itself. However, when designing the

low pass filter, the optimum load impedance for the amplifier should be taken into consideration as well. Between

the low pass filter and the ADC input the sampling glitch filter needs to added as well as shown in Section

8.3.1.2.1. In this example the DC - 30 MHz glitch filter is selected.

9.1.2.2 Sampling Clock

Applications operating with low input frequencies (such as DC to 20 MHz) typically are less sensitive to

performance degradation due to clock jitter. The internal ADC aperture jitter improves with faster rise and fall

times (i.e. square wave vs sine wave). Table 9-4 provides an overview of the estimated SNR performance of the

ADC364x based on different amounts of jitter of the external clock source. The SNR is estimated based on

ADC364x thermal noise of 79 dBFS and input signal at -1dBFS.

Table 9-4. ADC SNR performance across vs input frequency for different amounts of external clock jitter

INPUT FREQUENCY

TJ,EXT = 100 fs

TJ,EXT = 250 fs

TJ,EXT = 500 fs

TJ,EXT = 1 ps

5 MHz

79.0

78.9

78.7

10 MHz

79.0

78.9

78.7

78.0

20 MHz

78.8

78.6

77.9

75.9

Termination of the clock input should be considered for long clock traces.

9.1.2.3 Voltage Reference

The ADC364x is configured to internal reference operation by applying 0.6 V to the REFBUF pin.

ADC3643

SBAS886 – OCTOBER 2020

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