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ADC3641 датащи(PDF) 53 Page - Texas Instruments

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номер детали ADC3641
подробное описание детали  ADC364x 14-bit, 10-MSPS to 65-MSPS, Low-Noise, Low Power Dual Channel ADC
PDF  77 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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ADC3641 датащи(HTML) 53 Page - Texas Instruments

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Figure 8-53. Register 0x19
7
6
5
4
3
2
1
0
FCLK SRC
0
0
FCLK DIV
0
0
FCLK EN
TOG FCLK
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-24. Register 0x19 Field Descriptions
Bit
Field
Type
Reset
Description
7
FCLK SRC
R/W
0
User has to select if FCLK signal comes from ADC or from DDC
block. Here real decimation is treated same as bypass mode
0: FCLK generated from ADC. FCLK SRC set to 0 for DDC
bypass, real decimation mode and 1/2-w complex decimation
mode.
1: FCLK generated from DDC block. In complex decimation
mode only this bit needs to be set for 2-w and 1-w output
interface mode but NOT for 1/2-w mode.
6-5
0
R/W
0
Must write 0
4
FCLK DIV
R/W
0
This bit needs to be set to 1 for 2-w output mode in bypass
mode only (non decimation).
0: All output interface modes except 2-w bypass mode..
1: 2-w output interface mode.
3-2
0
R/W
0
Must write 0
1
FCLK EN
R/W
0
This bit enables FCLK output for CMOS output.
0: Data output pin is used for parallel output data.
1: Data output pin is used for FCLK output in serialized CMOS
mode.
0
TOG FCLK
R/W
0
This bit adjusts the FCLK signal appropriately for 1/2-wire mode
where FCLK is stretched to cover channel A and channel B.
This bit ONLY needs to be set in 1/2-wire mode with complex
decimation mode.
0: all other modes.
1: FCLK for 1/2-wire complex decimation mode.
Table 8-25. Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface
BYPASS/DECIMATION
SERIAL INTERFACE
FCLK SRC
FCLK DIV
TOG FCLK
Decimation Bypass/ Real Decimation
2-wire
0
1
0
1-wire
0
0
0
1/2-wire
0
0
0
Complex Decimation
2-wire
1
0
0
1-wire
1
0
0
1/2-wire
0
0
1
www.ti.com
ADC3643
SBAS886 – OCTOBER 2020
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: ADC3643



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