ADC3641 datasheet(59/77 Pages) TI

59 / 77 page

Table 8-36. OP-ORDER and Q-DELAY Register Settings for Complex Decimation

SCMOS INTERFACE

OP-ORDER

Q-DELAY

2-wire

1-wire

1/2-wire

Figure 8-63. Register 0x2A/B/C/D

NCO A [7:0]

NCO A [15:8]

NCO A [23:16]

NCO A [31:24]

R/W-0

Table 8-37. Register 0x2A/2B/2C/2D Field Descriptions

Bit

Field

Type

Reset

Description

7-0

NCO A [31:0]

R/W

Sets the 32 bit NCO value for decimation filter channel A. The

NCO value is fNCO× 232/FS

In real decimation mode these registers are automatically set to

Figure 8-64. Register 0x2E/2F/30

OP ORDER B

Q-DEL B

FS/4 MIX PH B

R/W-0

Table 8-38. Register 0x2E/2F/30 Field Descriptions

Bit

Field

Type

Reset

Description

7-5

R/W

Must write 0

OP ORDER B

R/W

Swaps the I and Q output order for channel B. See Table 8-36

for recommended settings. Only used with complex decimation.

Set to 0 with real decimation.

0: Output order is I[n], Q[n]

1: Output order is swapped: Q[n], I[n]

Q-DEL B

R/W

This delays the Q-sample output of channel B by one. See Table

8-36 for recommended settings. Only used with complex

decimation. Set to 0 with real decimation.

0: Output order is I[n], Q[n]

1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]

FS/4 MIX PH B

R/W

Inverts the mixer phase for channel B when using FS/4 mixer

0: Mixer phase is non-inverted

1: Mixer phase is inverted

1-0

R/W

Must write 0

www.ti.com

ADC3643

SBAS886 – OCTOBER 2020

Submit Document Feedback

Product Folder Links: ADC3643

ADC3641 датащи(PDF) 59 Page - Texas Instruments

ADC3641 датащи(HTML) 59 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

датащи скачать

ссылки URL