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ADC3641 датащи(PDF) 48 Page - Texas Instruments

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номер детали ADC3641
подробное описание детали  ADC364x 14-bit, 10-MSPS to 65-MSPS, Low-Noise, Low Power Dual Channel ADC
PDF  77 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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ADC3641 датащи(HTML) 48 Page - Texas Instruments

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Figure 8-46. Register 0x0A/B/C
7
6
5
4
3
2
1
0
CMOS OB DIS [23:0]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-16. Register 0x0A/B/C Field Descriptions
Bit
Field
Type
Reset
Description
7:0
CMOS OB DIS [23:0]
R/W
0
These register bits power down the individual CMOS output
buffers. See Table 8-17 for the actual bit to pin mapping. Unused
pins should be powered down (ie set to 1) for maximum power
savings. Even though unused outputs don't toggle there is still a
small amount of static power (< 1mA) that can be saved by
disabling the output buffers.
There is a separate control to enable the DCLKIN buffer in
register 0x1F (D6) and 0x18 (D4). DCLK output buffer is
powered down using register 0x1F (D4).
NOTE: When using serial CMOS interface the CMOS output
buffer (0x0A, D3 (DB1)) has to be powered down because it
shares the pin with DCLKIN.
0: Output buffer enabled
1: Output buffer powered down
Table 8-17. Output buffer enable bit mapping vs output interface mode
ADDRESS (HEX)
BIT
PIN NAME
DDR CMOS
SCMOS 2-w
SCMOS 1-w
SCMOS 1/2-w
0x0A
D7
DB5
DB5
DB5
-
-
D6
DB4
DB4
-
-
-
D5
-
-
-
-
-
D4
DB2
DB2
-
-
-
D3
DB1
DB1
DCLKIN
DCLKIN
DCLKIN
D2
DB0
DB0
-
-
-
D1/D0
-
-
-
-
-
Register setting
0x23
0x7F
0xFF
0xFF
0x0B
D7
DA4
DA4
-
-
-
D6
-
-
-
-
-
D5
DA2
DA2
-
-
-
D4
DA1
DA1
FCLK
FCLK
FCLK
D3
DA0
DA0
-
-
-
D2/D1
-
-
-
-
-
D0
DB6
DB6
DB6
DB6
-
Register setting
0x46
0xEE
0xEE
0xEF
0x0C
D7/D6/D5/D4
-
-
-
-
-
D3
DA3
DA3
-
-
-
D2
DB3
DB3
-
-
-
D1
DA6
DA6
DA6
DA6
DA6
D0
DA5
DA5
DA5
-
-
Register setting
0xF0
0xFC
0xFD
0xFD
ADC3643
SBAS886 – OCTOBER 2020
www.ti.com
48
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: ADC3643



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