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ADC3641 датащи(PDF) 57 Page - Texas Instruments

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номер детали ADC3641
подробное описание детали  ADC364x 14-bit, 10-MSPS to 65-MSPS, Low-Noise, Low Power Dual Channel ADC
PDF  77 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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ADC3641 датащи(HTML) 57 Page - Texas Instruments

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Figure 8-60. Register 0x25
7
6
5
4
3
2
1
0
DDC MUX EN
DECIMATION
REAL OUT
0
0
MIX PHASE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-33. Register 0x25 Field Descriptions
Bit
Field
Type
Reset
Description
7
DDC MUX EN
R/W
0
Enables the digital mux between ADCs and decimation filters.
This bit is required for DDC mux settings in register 0x024 (D4,
D3) to go into effect.
0: DDC mux disabled
1: DDC mux enabled
6-4
DECIMATION
R/W
000
Complex decimation setting. This applies to both channels.
000: Bypass mode (no decimation)
001: Decimation by 2
010: Decimation by 4
011: Decimation by 8
100: Decimation by 16
101: Decimation by 32
others: not used
3
REAL OUT
R/W
0
This bit selects real output decimation. This mode applies to
both channels. In this mode, the decimation filter is a low pass
filter and no complex mixing is performed to reduce power
consumption. For maximum power savings the NCO in this case
should be set to 0.
0: Complex decimation
1: Real decimation
2-1
0
R/W
0
Must write 0
0
MIX PHASE
R/W
0
This bit used to invert the NCO phase
0: NCO phase as is.
1: NCO phase inverted.
www.ti.com
ADC3643
SBAS886 – OCTOBER 2020
Copyright © 2020 Texas Instruments Incorporated
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