LP8733 datasheet(30/85 Pages) TI

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LP8733-Q1

SNVSB64 – SEPTEMBER 2018

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Regulator output voltage monitoring (not current limit monitoring) can be selected for PGOOD indication. This

selection is individual for both buck regulators (only master buck in dual-phase configuration) and both LDO

regulators and is set by EN_PGOOD_BUCKx bits in PGOOD_CTRL_1 register and EN_PGOOD_LDOx bits in

PGOOD_CTRL_1 register. When a regulator is disabled, the monitoring is automatically masked to prevent it

forcing

PGOOD

inactive.

thermal

warning

can

also

selected

for

PGOOD

indication

with

EN_PGOOD_TWARN bit in PGOOD_CTRL_2 register. The monitoring from all the output rails, thermal warning

(TDIE_WARN_STAT), input overvoltage interrupt (OVP_INT), and thermal shutdown interrupt (TDIE_SD_INT)

are combined, and PGOOD pin is active only if all the selected sources shows a valid status.

The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW_x bits in

PGOOD_CTRL_1 register. If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and

overvoltage are monitored.

The polarity and the output type (push-pull or open-drain) are selected by the PGOOD_POL and PGOOD_OD

bits in the PGOOD_CTRL_1 register.

PGOOD is only active or asserted when all enabled power resource output voltages are within specified

tolerance for each requested/programmed output voltage.

PGOOD is inactive or de-asserted if any enabled power resource output voltages is outside specified tolerance

for each requested/programmed output voltage.

The device OTP setting selects either gated (that is, unusual) or continuous (that is, invalid) mode of operation.

7.3.8.1.1

PGOOD Pin Gated mode

The gated (or unusual) mode of operation is selected by setting PGOOD_MODE bit to 0 in PGOOD_CTRL_2

For the gated mode of operation, PGOOD behaves as follows:

•

PGOOD is set to active or asserted state upon exiting OTP configuration as an initial default state.

•

PGOOD status is suspended or unchanged during an 800-µs gated time period, thereby gating-off the status

indication.

•

During normal power-up sequencing and requested voltage changes, PGOOD state is not changed during an

800-µs gated time period. It typically remains active or asserted for normal conditions.

•

During an abnormal power-up sequencing and requested voltage changes, PGOOD status could change to

inactive or de-asserted after an 800-µs gated time period if any output voltage is outside of regulation range.

•

Using the gated mode of operation could allow the PGOOD signal to initiate an immediate power shutdown

sequence if the PGOOD signal is wired-OR with signal connected to EN input. This type of circuit

configuration provides a smart PORz function for processor that eliminates the need for additional

components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.

The fault sets corresponding fault bit 1 in PG_FAULT register. The detected fault must be cleared to continue the

PGOOD monitoring. The overvoltage and thermal shutdown are cleared by writing 1 to the OVP_INT and

TDIE_SD_INT interrupt bits in INT_TOP_1 register. The regulator fault is cleared by writing 1 to the

corresponding register bit in PG_FAULT register. The interrupts can be also cleared with VANA UVLO by

toggling the input supply. An example of PGOOD pin operation in gated mode is shown in Figure 17.

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