LP8733 datasheet(28/85 Pages) TI

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LP8733-Q1

SNVSB64 – SEPTEMBER 2018

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7.3.7 Device Reset Scenarios

There are three reset methods implemented on the LP8733xx-Q1:

•

Software reset with SW_RESET bit in RESET register

•

Undervoltage lockout (UVLO) reset from VANA supply

An SW reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event

disables all the regulators immediately, drives GPO and GPO2 signals low, resets all the register bits to the

default values and OTP bits are loaded (see Figure 22). I2C interface is not reset during software reset.

If VANA supply voltage falls below the UVLO threshold level then all the regulators are disabled immediately,

GPO and GPO2 signals are driven low, and all the register bits are reset to the default values. When the VANA

supply voltage transition above UVLO threshold level an internal POR occurs. OTP bits are loaded to the

registers and a startup is initiated according to the register settings.

7.3.8 Diagnosis and Protection Features

The LP8733xx-Q1 is capable of providing four levels of protection features:

•

Information of valid regulator output voltage which sets interrupt or PGOOD signal;

•

Warnings for diagnosis which sets interrupt;

•

Protection events which are disabling the regulators; and

•

Faults which are causing the device to shutdown.

The LP8733xx-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT

pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the

pending interrupts are cleared.

When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in

INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, the interrupt is

not generated. The mask bit change with I2C does not affect, because the RESET_REG_MASK bit is loaded

from OTP during reset sequence.

LP8733 датащи(PDF) 28 Page - Texas Instruments