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LP8733 датащи(PDF) 51 Page - Texas Instruments |
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LP8733 датащи(HTML) 51 Page - Texas Instruments |
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51 / 85 page ![]() 51 LP8733-Q1 www.ti.com SNVSB64 – SEPTEMBER 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 7.6.1.20 CONFIG Address: 0x13 D7 D6 D5 D4 D3 D2 D1 D0 Reserved STARTUP_DE LAY_SEL SHUTDOWN_ DELAY_SEL CLKIN_PIN_SE L CLKIN_PD EN2_PD TDIE_WARN_ LEVEL EN_SPREAD _SPEC Bits Field Type Default Description 7 Reserved R/W 0 6 STARTUP_DELAY _SEL R/W X Startup delay range from EN signals. 0 - 0 ms - 7.5 ms with 0.5 ms steps 1 - 0 ms - 15 ms with 1 ms steps 5 SHUTDOWN_DEL AY_SEL R/W X Shutdown delay range from EN signals. 0 - 0 ms - 7.5 ms with 0.5 ms steps 1 - 0 ms - 15 ms with 1 ms steps 4 CLKIN_PIN_SEL R/W X CLKIN pin function: 0 - GPO2 1 - CLKIN 3 CLKIN_PD R/W X Selects the pull down resistor on the CLKIN input pin. (valid also when selected as GPO2) 0 - Pull-down resistor is disabled. 1 - Pull-down resistor is enabled. 2 EN_PD R/W X Selects the pull down resistor on the EN input pin. 0 - Pull-down resistor is disabled. 1 - Pull-down resistor is enabled. 1 TDIE_WARN_ LEVEL R/W X Thermal warning threshold level. 0 - 125°C 1 - 137°C. 0 EN_SPREAD _SPEC R/W X Enable spread spectrum feature: 0 - Disabled 1 - Enabled 7.6.1.21 PLL_CTRL Address: 0x14 D7 D6 D5 D4 D3 D2 D1 D0 Reserved EN_PLL Reserved EXT_CLK_FREQ[4:0] Bits Field Type Default Description 7 Reserved R/W 0 6 EN_PLL R/W X Selection of external clock and PLL operation: 0 - Forced to internal RC oscillator. PLL disabled. 1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use when available, interrupt generated if external clock appears or disappears. 5 Reserved R/W 0 This bit must be set to '0'. 4:0 EXT_CLK_FREQ[4 :0] R/W X Frequency of the external clock (CLKIN): 0x00 - 1 MHz 0x01 - 2 MHz 0x02 - 3 MHz ... 0x16 - 23 MHz 0x17 - 24 MHz 0x18...0x1F - Reserved See electrical specification for input clock frequency tolerance. |
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