LP8733 datasheet(73/85 Pages) TI

73 / 85 page

LP8733-Q1

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SNVSB64 – SEPTEMBER 2018

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Figure 78. LDO VOUT Transition from 1.2 V to 1.8 V

Start-up

delay is 500

µs

Figure 79. LDO Start-Up With Short on Output

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.8 V and 5.5 V. The VANA input

and VIN_Bx buck inputs must be connected together, and they must use the same input supply. This input

supply must be well regulated and able to withstand maximum input current and maintain stable voltage without

voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the

input current transient does not cause too high a drop in the LP8733xx-Q1 supply voltage that can cause false

UVLO fault triggering. If the input supply is located more than a few inches from the LP8733xx-Q1 additional bulk

capacitance may be required in addition to the ceramic bypass capacitors. The VIN_LDOx LDO input supply

voltage range is 2.5 V to 5.5 V and can be higher or lower than VANA supply voltage.

10 Layout

10.1 Layout Guidelines

The high frequency and large switching currents of the LP8733xx-Q1 make the choice of layout important. Good

power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and

generation and can cause a good design to perform with less-than-expected results. With a range of output

currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB

design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and

current regulation across its intended operating voltage and current range.

1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the VIN trace wide and thick

to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of

LP8733xx-Q1, as well as the trace between the negative node of the input capacitor and power PGND_Bx

pin(s), must be kept as short as possible. The input capacitance provides a low-impedance voltage source

for the switching converter. The inductance of the connection is the most important parameter of a local

decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for proper

device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to

top layer by using thin dielectric layer between top layer and ground plane.

2. The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output

voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI

behavior. Route the traces between the output capacitors of the LP8733xx-Q1 and the input capacitors of the

load direct and wide to avoid losses due to the IR drop.

3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a

quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling

capacitor as close as possible to the VANA pin.

LP8733 датащи(PDF) 73 Page - Texas Instruments