LP8733 datasheet(22/85 Pages) TI

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24MHz

Oscillator

CLKIN

Divider

´(;7_CLK_

)5(4´

PLL

Divider

CLKIN

Detector

Clock Select

Logic

Internal

24MHz

clock

1MHz

´(1_3//´

24MHz

LP8733-Q1

SNVSB64 – SEPTEMBER 2018

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Feature Description (continued)

Figure 12. Clock and PLL Module

Table 2. PLL Operation

DEVICE

OPERATION MODE

EN_PLL

PLL AND CLOCK

DETECTOR STATE

INTERRUPT FOR

EXTERNAL CLOCK

CLOCK

STANDBY

Disabled

Internal RC

ACTIVE

Disabled

Internal RC

STANDBY

Enabled

When external clock

appears or disappears

Automatic change to external

clock when available

ACTIVE

Enabled

When external clock

appears or disappears

Automatic change to external

clock when available

7.3.3 Low-Dropout Linear Regulators (LDOs)

The LP8733xx-Q1 device includes two identical linear regulators, LDO0 and LDO1, targeting analog loads with

low noise requirements. The LDO regulators deliver 0.8-V to 3.3-V regulated voltage rails from a 2.5-V to 5.5-V

input voltage. Both regulators have dedicated inputs which can be higher or lower than the device system voltage

V(VANA) to minimize the power dissipation.

7.3.4 Power-Up

The power-up sequence for the LP8733xx-Q1 is as follows:

•

VANA (and VIN_Bx) reach minimum recommended levels (VVANA > VANAUVLO). This initiates power-on-reset

(POR), OTP reading, and enables the system I/O interface. The I2C host should allow at least 1.2 ms before

writing or reading data to the LP8733xx-Q1.

•

Device enters standby mode.

•

The host can change the default register setting by I2C if needed.

•

The regulators can be enabled/disabled and the GPO signals can be controlled by EN pin and by I2C

interface.

Transitions between the operating modes are shown in Modes of Operation.

7.3.5 Regulator Control

7.3.5.1 Enabling and Disabling Regulators

The regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways for enable

and disable the buck regulators:

•

Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 0 in BUCKx_CTRL_1

•

Using EN control pin (BUCKx_EN bit is 1 AND BUCKx_EN_PIN_CTRL bit is 1)

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