LP8733 datasheet(53/85 Pages) TI

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LP8733-Q1

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SNVSB64 – SEPTEMBER 2018

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Bits

Field

Type

Default

Description

7:4

Reserved

R/W

0000

PG_FAULT_LDO1

R/W

Source for PGOOD inactive signal:

0 - LDO1 has not set PGOOD signal inactive.

1 - LDO1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit

can be cleared by writing '1' to this bit when LDO1 output is valid.

PG_FAULT_LDO0

R/W

Source for PGOOD inactive signal:

0 - LDO0 has not set PGOOD signal inactive.

1 - LDO0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit

can be cleared by writing '1' to this bit when LDO0 output is valid.

PG_FAULT_BUCK

R/W

Source for PGOOD inactive signal:

0 - Buck1 has not set PGOOD signal inactive.

1 - Buck1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit

can be cleared by writing '1' to this bit when Buck1 output is valid.

PG_FAULT_BUCK

R/W

Source for PGOOD inactive signal:

0 - Buck0 has not set PGOOD signal inactive.

1 - Buck0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit

can be cleared by writing '1' to this bit when Buck0 output is valid.

7.6.1.25 RESET

Address: 0x18

Reserved

SW_RESET

Bits

Field

Type

Default

Description

7:1

Reserved

R/W

000 0000

SW_RESET

R/W

Software commanded reset. When written to 1, the registers will be reset to default

values, OTP memory is read, and the I2C interface is reset.

The bit is automatically cleared.

7.6.1.26 INT_TOP_1

Address: 0x19

PGOOD_INT

LDO_INT

BUCK_INT

SYNC_CLK_IN

TDIE_SD_INT

TDIE_WARN_I

OVP_INT

I_MEAS_INT

Bits

Field

Type

Default

Description

PGOOD_INT

R/W

Latched status bit indicating that the PGOOD pin has changed from active to inactive.

Write 1 to clear interrupt.

LDO_INT

Interrupt indicating that LDO1 and/or LDO0 have a pending interrupt. The reason for

the interrupt is indicated in INT_LDO register.

This bit is cleared automatically when INT_LDO register is cleared to 0x00.

BUCK_INT

Interrupt indicating that Buck1 and/or Buck0 have a pending interrupt. The reason for

the interrupt is indicated in INT_BUCK register.

This bit is cleared automatically when INT_BUCK register is cleared to 0x00.

SYNC_CLK_INT

R/W

Latched status bit indicating that the external clock has appeared or disappeared.

Write 1 to clear interrupt.

TDIE_SD_INT

R/W

Latched status bit indicating that the die junction temperature has exceeded the

thermal shutdown level. The regulators have been disabled if they were enabled and

GPO and GPO2 signals are driven low. The regulators cannot be enabled if this bit is

active. The actual status of the thermal shutdown is indicated by TDIE_SD_STAT bit in

TOP_STAT register.

Write 1 to clear interrupt.

TDIE_WARN_INT

R/W

Latched status bit indicating that the die junction temperature has exceeded the

thermal warning level. The actual status of the thermal warning is indicated by

TDIE_WARN_STAT bit in TOP_STAT register.

Write 1 to clear interrupt.

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