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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP8733 датащи(PDF) 54 Page - Texas Instruments |
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LP8733 датащи(HTML) 54 Page - Texas Instruments |
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54 / 85 page  54 LP8733-Q1 SNVSB64 – SEPTEMBER 2018 www.ti.com Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Bits Field Type Default Description 1 OVP_INT R/W 0 Latched status bit indicating that the input voltage has exceeded the over-voltage detection level. The regulators have been disabled if they were enabled and GPO and GPO2 signals are driven low. The actual status of the over-voltage is indicated by OVP_STAT bit in TOP_STAT register. Write 1 to clear interrupt. 0 I_MEAS_INT R/W 0 Latched status bit indicating that the load current measurement result is available in I_LOAD_1 and I_LOAD_2 registers. Write 1 to clear interrupt. 7.6.1.27 INT_TOP_2 Address: 0x1A D7 D6 D5 D4 D3 D2 D1 D0 Reserved RESET_REG_I NT Bits Field Type Default Description 7:1 Reserved R/W 000 0000 0 RESET_REG_INT R/W 0 Latched status bit indicating that either VANA supply voltage has been below undervoltage threshold level or the host has requested a reset using SW_RESET bit in RESET register. The regulators have been disabled, and registers are reset to default values and the normal startup procedure is done. Write 1 to clear interrupt. 7.6.1.28 INT_BUCK Address: 0x1B D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK1_PG _INT BUCK1_SC _INT BUCK1_ILIM _INT Reserved BUCK0_PG _INT BUCK0_SC _INT BUCK0_ILIM _INT Bits Field Type Default Description 7 Reserved R/W 0 6 BUCK1_PG_INT R/W 0 Latched status bit indicating that Buck1 Power-Good event has been detected. Write 1 to clear. 5 BUCK1_SC_INT R/W 0 Latched status bit indicating that the Buck1 output voltage has been over 1 ms below short-circuit threshold level. Write 1 to clear. 4 BUCK1_ILIM_INT R/W 0 Latched status bit indicating that the Buck1 output current limit has been active. Write 1 to clear. 3 Reserved R/W 0 2 BUCK0_PG_INT R/W 0 Latched status bit indicating that Buck0 Power-Good event has been detected. Write 1 to clear. 1 BUCK0_SC_INT R/W 0 Latched status bit indicating that the Buck0 output voltage has been over 1 ms below short-circuit threshold level. Write 1 to clear. 0 BUCK0_ILIM_INT R/W 0 Latched status bit indicating that the Buck0 output current limit has been active. Write 1 to clear. 7.6.1.29 INT_LDO Address: 0x1C D7 D6 D5 D4 D3 D2 D1 D0 Reserved LDO1_PG _INT LDO1_SC _INT LDO1_ILIM _INT Reserved LDO0_PG _INT LDO0_SC _INT LDO0_ILIM _INT |
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