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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP8733 датащи(PDF) 25 Page - Texas Instruments |
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LP8733 датащи(HTML) 25 Page - Texas Instruments |
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25 / 85 page  Enable Time Voltage Resistive pull-down (if enabled) LDOx_VSET[4:0] INT_LDO(LDOx_PG_INT) nINT Host clears interrupts Powergood interrupts Powergood LDO_STAT(LDOx_PG_STAT) 0 0 1 Voltage decrease because of load LDO_STAT(LDOx_STAT) 0 0 1 0 1 1 0 0 1 0 1 0 LDO_MASK(LDOx_PGF_MASK) = 0 LDO_MASK(LDOx_PGR_MASK) = 0 1 0 25 LP8733-Q1 www.ti.com SNVSB64 – SEPTEMBER 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Figure 14. LDO Regulator Enable and Disable The EN input pin have an integrated pulldown resistor. The pulldown resistor is controlled with EN_PD bit in CONFIG register. 7.3.5.2 Changing Output Voltage The output voltage of the regulator can be changed by writing to the BUCKx_VOUT / LDOx_VOUT register. The voltage change for buck regulator is always slew-rate controlled, and the slew-rate is defined by the BUCKx_SLEW_RATE[2:0] bits in BUCKx_CTRL_2 register. During voltage change the forced PWM mode is used automatically. If the dual-phase operation is forced by the BUCK0_FPWM_MP bit in BUCK0_CTRL_1 register, the regulator operates in dual-phase mode. If the dual-phase operation is not forced, the number of phases are added and shedded automatically to follow the required slew rate. When the programmed output voltage is achieved, the mode becomes the one defined by load current, and the BUCKx_FPWM bit in BUCKx_CTRL_1 register and by BUCK0_FPWM_MP bit. The voltage change and Power-Good interrupts are shown in Figure 15. |
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