UPD360 datasheet(169/221 Pages) MICROCHIP

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 2016-2017 Microchip Technology Inc.

DS00002084C-page 169

UPD360

11.4.5.2

BIST Control Register B (BIST_CTL_B)

Address:

1AC1h

Size:

8 bits

Bits

Description

Type

Default

7:3

RESERVED

BIST_CLR_ERR_CNT

Clears the BIST error count registers BIST Error Count High Register

(BIST_ERR_CNT_HI) and BIST Error Count Low Register (BIST_ER-

R_CNT_LO).

BIST_TX_RST

Reset the TX logic and PRBS generator. Software must set this bit once

before starting the BIST test, i.e., setting BIST_TX_START/BIST_TX_STA-

TUS bit for the first time.

Since this bit resets the PRBS generator it should not be set again until the

current BIST test is ended.

This bit is not latched and will always read '0'

The PRBS generator cannot be reset by BIST_TX_START/BIST_TX_STA-

TUS because that would reset it for each TX BIST frame.

This bit should be used to stop the continuous BIST TX mode (2). It may take

up to 1 bit time for the TX to stop. BIST_EN should not be cleared until after

this time.

Note:

If this bit is set simultaneously with BIST_TX_START/BIST_TX-

_STATUS, it takes precedence and will void BIST_TX_START/

BIST_TX_STATUS.

BIST_TX_START/BIST_TX_STATUS

Start BIST transmission. Setting this bit will trigger transmission of BIST

frame.

This bit is not latched and reading it will return the status of current BIST

transmission.

Depending on BIST Mode, transmission will either continue indefinitely

(unless BIST_TX_RST is asserted) or stop after sending a BIST PRBS frame.

BIST does not support sending of next BIST frame automatically. It must be

triggered by software by first clearing and then re-setting this bit.

Note:

This bit cannot be set simultaneously with BIST_TX_RST.

BIST_TX_RST has precedence and will void BIST_TX_START/

BIST_TX_STATUS.

In BIST RX mode, hardware will automatically send the BIST Error Count

message if the EN_AUTO_RSP_MODE bit in the TX Control Register A

(TX_CTL_A) is set.

WO/RO

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