UPD360 datasheet(168/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 168

 2016-2017 Microchip Technology Inc.

11.4.5

PD MAC BIST REGISTERS

The following sub-sections describe the various registers associated with the PD MAC Built-In Self Test (BIST).

11.4.5.1

BIST Control Register A (BIST_CTL_A)

Address:

1AC0h

Size:

8 bits

Bits

Description

Type

Default

7:5

RESERVED

BIST_RX_EN

Enable BIST Receiver.

Setting this bit will:

• Enable the BIST receiver.

• Reset the PRBS generator in the BIST RX logic so it is ready to compare

incoming BIST PRBS pattern.

• Reset the BIST error count registers (BIST Error Count High Register

(BIST_ERR_CNT_HI) and BIST Error Count Low Register (BIST_ER-

R_CNT_LO).

Normally this bit is set only when BIST receiver mode is required; however,

this bit can be set to enable loopback BIST testing by disabling Automatic

Response Mode and enabling the RX loopback (setting the EN_LOOPBACK

bit in the RX Control Register A (RX_CTL_A)).

This bit must be cleared and set by software every time a new BIST RX

request comes in.

Note:

In BIST loopback test mode, BIST TX must be manually triggered

for each TX packet since functional receiver path is disabled.

R/W

BIST_EN

Enable BIST. Set this bit when BIST logic is activated.

This bit together with the EN_LOOPBACK bit in the RX Control Register A

(RX_CTL_A) is used by hardware to block received data from going into func-

tional path. This means that when loopback is enabled in BIST mode hard-

ware cannot detect hard reset.

This bit also powers up the BMC transmitter for BIST mode operation. Soft-

ware should set this bit for a sufficient amount of time (5us) before trigger

transmission of BIST frame via BIST_TX_START/BIST_TX_STATUS.

R/W

2:0

BIST_TX_MODE

Set BIST Test Mode. Only the following mode is supported:

010b: BIST Carrier Test Mode-2 (alternating '1's and '0's)

All other modes are reserved and should not be used.

R/W

000b

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