UPD360 datasheet(141/221 Pages) MICROCHIP

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 2016-2017 Microchip Technology Inc.

DS00002084C-page 141

UPD360

11.4.2

PD MAC RX REGISTERS

The following sub-sections describe the various registers associated with the PD MAC RX logic.

11.4.2.1

RX Control Register A (RX_CTL_A)

Address:

1A40h

Size:

8 bits

Bits

Description

Type

Default

7:6

RESERVED

EN_LOOPBACK

Enable loopback. This bit allows the MAC to receive its own transmission.

Note:

Loopback happens at the pin where TX and RX are connected

together.

R/W

EN_RCV

Enable Receiver. Software should set this bit when it is done configuring the

receiver. Setting this bit will enable the receiver to start normal operation.

If this bit is set while receive activity is in progress it will take effect after cur-

rent receive activity is over. If this bit is cleared while a receive is being pro-

cessed it will take effect after current receive is finished.

This bit will be automatically cleared by hardware upon reception of Hard

Reset or a Cable Reset to prevent normal packet reception.

After POR or SW_RESET, Hard and Cable Reset reception is disabled until

EN_RCV is set. Thereafter, clearing of EN_RCV (by software or hardware)

has no impact to reception of Hard or Cable Reset, i.e., hardware will process

Hard or Cable Reset even with EN_RCV cleared.

If software wishes to re-initialize receive timing parameters after EN_RCV has

been set once it must first reset the UPD_MAC_v2 using SW_RESET.

This bit is not reset by assertion of PD_RESET.

R/W

RST_RECEIVER

Setting this bit will reset the receiver Queue. Software should set this bit if

receiver hardware may be out of sync with software. Hardware latches this bit

so it must be cleared by software to resume receiver operation. Receiver

hardware is also reset when PD_RESET bit in RESET_CTL register is set.

R/W

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