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82801E датащи(PDF) 53 Page - Intel Corporation

номер детали 82801E
подробное описание детали  Intel 82801E Communications I/O Controller Hub (C-ICH)
PDF  84 Pages
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

82801E датащи(HTML) 53 Page - Intel Corporation

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Intel® 82801E C-ICH
Advance Information Datasheet
53
3.4.4
Output and I/O Signals Planes and States
Table 32 shows the power plane associated with the output and I/O signals, as well as the state at
various times. Within the table, the following terms are used:
“High-Z”
Tri-state. 82801E C-ICH not driving the signal high or low.
“High”
The 82801E C-ICH is driving the signal to a logic ‘1’.
“Low”
The 82801E C-ICH is driving the signal to a logic ‘0’.
“Defined”
The signal is driven to a level that is defined by the function (will be high or low).
“Undefined”
The 82801E C-ICH is driving the signal, but the value is indeterminate.
“Running”
The clock is toggling or signal is transitioning because function not stopping.
“Off”
The power plane is off; the 82801E C-ICH is not driving.
Table 32. Power Plane and States for Output and I/O Signals (Sheet 1 of 3)
Signal Name
Power Plane
Reset Signal
During Reset
Immediately
after Reset
PCI Bus
AD[31:0]
Main I/O
PCIRST#
High-Z
Undefined
C/BE#[3:0]
Main I/O
PCIRST#
High-Z
Undefined
DEVSEL#
Main I/O
PCIRST#
High-Z
High-Z
FRAME#
Main I/O
PCIRST#
High-Z
High-Z
GNT[3:0]#, GNT[5]#
Main I/O
PCIRST#
High
High
GNT[A:B]#
Main I/O
PCIRST#
High-Z
High
IRDY#, TRDY#
Main I/O
PCIRST#
High-Z
High-Z
PAR
Main I/O
PCIRST#
High-Z
Undefined
PCIRST#
Main I/O
RSMRST#
Low
High
PERR#
Main I/O
PCIRST#
High-Z
High-Z
PLOCK#
Main I/O
PCIRST#
High-Z
High-Z
STOP#
Main I/O
PCIRST#
High-Z
High-Z
LPC Interface
LAD[3:0]
Main I/O
PCIRST#
High
High
LFRAME#
Main I/O
PCIRST#
High
High
LAN Connect and EEPROM Interface
EE0_CS, EE1_CS
LAN I/O
RSM_PWROK
Low
Running
NOTES:
1. The 82801E C-ICH sets these signals at reset for processor frequency strap.
2. I GPIO[18] will toggle at a frequency of approximately 1 Hz when the 82801E C-ICH comes out of reset
3. CPUPWRGD is an open-drain output that represents a logical AND of the VRMPWRGD and PWROK
signals and, thus, are driven low by 82801E C-ICH when either VRMPWRGD or PWROK are inactive.
During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low
to High-Z.
4. GPIO[24:25, 27:28]: These signals remain tri-stated for up to 110 ms after RSMRST# deassertion. At this
point, they will be driven to their default (High) state.



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