82801E datasheet(29/84 Pages) INTEL

29 / 84 page

Intel® 82801E C-ICH

Advance Information Datasheet

LAN0_RXD[2:0]

LAN1_RXD[2:0]

Received Data: The LAN Connect component uses these signals to transfer

data and control information to the integrated LAN Controller. These signals

have integrated weak pull-up resistors.

LAN0_TXD[2:0]

LAN1_TXD[2:0]

Transmit Data: The integrated LAN Controller uses these signals to transfer

data and control information to the LAN Connect component.

LDRQ[1:0]#

LPC Serial DMA/Master Request Inputs: These signals are used to request

DMA or bus master access. Typically, they are connected to external Super

I/O device. An internal pull-up resistor is provided on these signals.

LFRAME#

/FWH[4]

LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.

NC[10:1]

—

No Connect. Do not connect these pins.

Optional: NC[10:6, 3:1] can be routed to a test point for use in manufacturing

NAND tree testing.

NMI

Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to

the processor. The 82801E C-ICH can generate an NMI when either SERR#

or IOCHK# is asserted. The processor detects an NMI when it detects a rising

edge on NMI. NMI is reset by setting the corresponding NMI source

enable/disable bit in the NMI Status and Control Register.

Speed Strap: During the reset sequence, 82801E C-ICH drives NMI high if

the corresponding bit is set in the FREQ_STRP register.

OC[1:0]#

Overcurrent Indicators: These signals set corresponding bits in the USB

controllers to indicate that an overcurrent condition has occurred.

PAR

I/O

Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits,

AD[31:0] plus C/BE[3:0]#. “Even” parity means that the 82801E C-ICH counts

the number of 1s within the 36 bits plus PAR and the sum is always even. The

82801E C-ICH always calculates PAR on 36 bits, regardless of the valid byte

enables. The 82801E C-ICH generates PAR for address and data phases and

only guarantees PAR to be valid one PCI clock after the corresponding

address or data phase. The 82801E C-ICH drives and tri-states PAR

identically to the AD[31:0] lines except that the 82801E C-ICH delays PAR by

exactly one PCI clock. PAR is an output during the address phase (delayed

one clock) for all 82801E C-ICH initiated transactions. PAR is an output

during the data phase (delayed one clock) when the 82801E C-ICH is the

Initiator of a PCI write transaction, and when it is the target of a read

transaction. 82801E C-ICH checks parity when it is the target of a PCI write

transaction. If a parity error is detected, the 82801E C-ICH sets the

appropriate internal status bits, and has the option to generate an NMI# or

SMI#.

PCICLK

PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all

transactions on the PCI Bus.

PCIRST#

PCI Reset: 82801E C-ICH asserts PCIRST# to reset devices that reside on

the PCI bus. The 82801E C-ICH asserts PCIRST# during power-up and when

S/W initiates a hard reset sequence through the RC (CF9h) register. The

82801E C-ICH drives PCIRST# inactive a minimum of 1 ms after PWROK is

driven active. The 82801E C-ICH drives PCIRST# active a minimum of 1 ms

when initiated through the RC register.

PDA[2:0]

Primary IDE Device Address: These output signals are connected to the

corresponding signals on the primary IDE connector. They are used to

indicate which byte in either the ATA command block or control block is being

addressed.

PDCS1#

Primary IDE Device Chip Selects for 100 Range: This signal is for the ATA

command register block. This output signal is connected to the corresponding

signal on the primary IDE connector.

Table 6.

82801E C-ICH Signal Description (Sheet 5 of 11)

Signal

Type

Description

82801E датащи(PDF) 29 Page - Intel Corporation

82801E датащи(HTML) 29 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

датащи скачать

ссылки URL