82801E datasheet(38/84 Pages) INTEL

38 / 84 page

Intel® 82801E C-ICH

Advance Information Datasheet

FRAME#

I/O

Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and

duration of a PCI transaction. While the initiator asserts FRAME#, data transfers

continue. When the initiator negates FRAME#, the transaction is in the final data

phase. FRAME# is an input to the 82801E C-ICH when the 82801E C-ICH is the

target, and FRAME# is an output from the 82801E C-ICH when the 82801E C-ICH

is the Initiator. FRAME# remains tri-stated by the 82801E C-ICH until driven by an

Initiator.

IRDY#

I/O

Initiator Ready: IRDY# indicates the 82801E C-ICH’s ability, as an Initiator, to

complete the current data phase of the transaction. It is used in conjunction with

TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are

sampled asserted. During a write, IRDY# indicates the 82801E C-ICH has valid

data present on AD[31:0]. During a read, it indicates the 82801E C-ICH is prepared

to latch data. IRDY# is an input to the 82801E C-ICH when the 82801E C-ICH is the

Target and an output from the 82801E C-ICH when the 82801E C-ICH is an

Initiator. IRDY# remains tri-stated by the 82801E C-ICH until driven by an Initiator.

TRDY#

I/O

Target Ready: TRDY# indicates the 82801E C-ICH’s ability as a Target to complete

the current data phase of the transaction. TRDY# is used in conjunction with

IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled

asserted. During a read, TRDY# indicates that the 82801E C-ICH, as a Target, has

placed valid data on AD[31:0]. During a write, TRDY# indicates the 82801E C-ICH,

as a Target is prepared to latch data. TRDY# is an input to the 82801E C-ICH when

the 82801E C-ICH is the Initiator and an output from the 82801E C-ICH when the

82801E C-ICH is a Target. TRDY# is tri-stated from the leading edge of PCIRST#.

TRDY# remains tri-stated by the 82801E C-ICH until driven by a target.

STOP#

I/O

Stop: STOP# indicates that the 82801E C-ICH, as a Target, is requesting the

Initiator to stop the current transaction. STOP# causes the 82801E C-ICH, as an

Initiator, to stop the current transaction. STOP# is an output when the 82801E

C-ICH is a target and an input when the 82801E C-ICH is an Initiator. STOP# is

tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated until driven

by the 82801E C-ICH.

PAR

I/O

Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits,

AD[31:0] plus C/BE[3:0]#. “Even” parity means that the 82801E C-ICH counts the

number of 1s within the 36 bits plus PAR and the sum is always even. The 82801E

C-ICH always calculates PAR on 36 bits, regardless of the valid byte enables. The

82801E C-ICH generates PAR for address and data phases and only guarantees

PAR to be valid one PCI clock after the corresponding address or data phase. The

82801E C-ICH drives and tri-states PAR identically to the AD[31:0] lines except that

the 82801E C-ICH delays PAR by exactly one PCI clock. PAR is an output during

the address phase (delayed one clock) for all 82801E C-ICH initiated transactions.

PAR is an output during the data phase (delayed one clock) when the 82801E

C-ICH is the Initiator of a PCI write transaction, and when it is the target of a read

transaction. 82801E C-ICH checks parity when it is the target of a PCI write

transaction. If a parity error is detected, the 82801E C-ICH sets the appropriate

internal status bits, and has the option to generate an NMI# or SMI#.

PERR#

I/O

Parity Error: An external PCI device drives PERR# when it receives data that has

a parity error. The 82801E C-ICH drives PERR# when it detects a parity error. The

ICH can either generate an NMI# or SMI# upon detecting a parity error (either

detected internally or reported via the PERR# signal).

REQ[3:0]#

/REQ[5]#

/REQ[B]#

/GPIO[1]

PCI Requests: The 82801E C-ICH supports up to five masters on the PCI bus.

REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the other, but not

both). If not used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be used as

GPIO[1].

NOTE: REQ[0]# is programmable to have improved arbitration latency for

supporting PCI-based 1394 controllers.

Table 11. PCI Interface Signals (Sheet 2 of 3)

Name

Type

Description

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