82801E datasheet(25/84 Pages) INTEL

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Intel® 82801E C-ICH

Advance Information Datasheet

3.0

Signal Descriptions

This section provides a detailed description of each signal. The signals are arranged in functional

groups according to their associated interface.

The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when

the signal is at a low voltage level. When “#” is not present, the signal is asserted when at the high

voltage level.

The following notations are used to describe the signal type:

Input pin

Output pin

Open drain output pin.

I/O

Bidirectional input/output pin.

3.1

Alphabetical Signal Reference

Table 6.

82801E C-ICH Signal Description (Sheet 1 of 11)

Signal

Type

Description

A20GATE

A20 Gate: This signal is from the keyboard controller. It acts as an alternative

method to force the A20M# signal active. A20GATE eliminates the need for

the external OR gate needed with various other PCIsets.

A20M#

Mask A20: A20M# goes active based on setting the appropriate bit in the

Port 92h register, or based on the A20GATE signal.

Speed Strap: During the reset sequence, 82801E C-ICH drives A20M# high

if the corresponding bit is set in the FREQ_STRP register.

AD[31:0]

I/O

PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During

the first clock of a transaction, AD[31:0] contain a physical address (32 bits).

During subsequent clocks, AD[31:0] contain data. The 82801E C-ICH drives

all 0s on AD[31:0] during the address phase of all PCI Special Cycles.

APICCLK

APIC Clock: The APIC clock runs at 33.333 MHz.

APICD[1:0]

I/OD

APIC Data: These bidirectional open drain signals are used to send and

receive data over the APIC bus. As inputs, the data is valid on the rising edge

of APICCLK. As outputs, new data is driven from the rising edge of the

APICCLK.

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