82801E datasheet(84/84 Pages) INTEL

84 / 84 page

Intel® 82801E C-ICH

Advance Information Datasheet

5.3.1

XOR Chain Testability Algorithm Example

XOR chain testing allows motherboard manufacturers to check component connectivity (e.g.,

opens and shorts to VCC or GND). An example algorithm to do this is shown in Table 62.

In this example, Vector 1 applies all “0s” to the chain inputs. The outputs being non-inverting, will

consistently produce a “1” at the XOR output on a good board. One short to Vcc (or open floating

to Vcc) will result in a “0” at the chain output, signaling a defect.

Likewise, applying Vector 7 (all “1s”) to the chain inputs (given that there are an even number of

input signals in the chain), will consistently produce a “1” at the XOR chain output on a good

board. One short to Vss (or open floating to Vss) will result in a “0” at the chain output, signaling a

defect. It is important to note that the number of inputs pulled to “1” will affect the expected chain

output value. If the number of chain inputs pulled to “1” is even, then expect “1” at the output. If

the number of chain inputs pulled to “1” is odd, expect “0” at the output.

Continuing with the example in Table 62, as the input pins are driven to “1” across the chain in

sequence, the XOR Output will toggle between “0” and “1.” Any break in the toggling sequence

(e.g., “1011”) will identify the location of the short or open.

5.3.1.1

Test Pattern Consideration for XOR Chain 4

When the 82801E C-ICH is operated with the Hub Interface in “Normal” mode (See “Functional

Straps” on page 49), the HL_STB and HL_STB# signals must always be driven to complementary

logic levels. For example, if a “1” is driven on HL_STB, then a “0” must be driven on HL_STB#

and vice versa. This will need to be considered in applying test patterns to this chain.

When the 82801E C-ICH is operated with the Hub Interface in “Enhanced” mode there are no

restrictions on the values that may be driven onto the HL_STB and HL_STB# signals.

Table 62. XOR Test Pattern Example

Vector

Input

Pin 1

Input

Pin 2

Input

Pin 3

Input

Pin 4

Input

Pin 5

Input

Pin 6

XOR

Output

82801E датащи(PDF) 84 Page - Intel Corporation

82801E датащи(HTML) 84 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

датащи скачать

ссылки URL