82801E datasheet(4/84 Pages) INTEL

4 / 84 page

Contents

Advance Information Datasheet

4.2

Functional Operating Range............................................................................................... 57

4.3

DC Characteristics.............................................................................................................. 58

4.4

AC Characteristics .............................................................................................................. 62

4.5

Timing Diagrams................................................................................................................. 70

5.0

Testability..................................................................................................................................... 77

5.1

Test Mode Description........................................................................................................77

5.2

Tri-state Mode..................................................................................................................... 78

5.3

XOR Chain Mode................................................................................................................ 78

5.3.1

XOR Chain Testability Algorithm Example ............................................................ 84

5.3.1.1

Test Pattern Consideration for XOR Chain 4......................................... 84

Figures

System Configuration ................................................................................................................... 7

2Intel® 82801E C-ICH Simplified Block Diagram ........................................................................... 8

Ball Diagram (Top View)............................................................................................................. 11

4Intel® 82801E C-ICH Package (Top View) ................................................................................. 23

5Intel® 82801E C-ICH Package (Side View) ................................................................................ 24

6Intel® 82801E C-ICH Package (Bottom View)............................................................................ 24

Required External RTC Circuit ................................................................................................... 50

Example V5REF Sequencing Circuit .......................................................................................... 51

Clock Timing ............................................................................................................................... 70

Valid Delay From Rising Clock Edge.......................................................................................... 70

Setup And Hold Times................................................................................................................ 71

Float Delay ................................................................................................................................. 71

Pulse Width ................................................................................................................................ 71

Output Enable Delay .................................................................................................................. 71

IDE PIO Mode ............................................................................................................................ 72

IDE Multiword DMA .................................................................................................................... 72

Ultra ATA Mode (Drive Initiating a Burst Read) .......................................................................... 73

Ultra ATA Mode (Sustained Burst) ............................................................................................. 73

Ultra ATA Mode (Pausing a DMA Burst) .................................................................................... 74

Ultra ATA Mode (Terminating a DMA Burst) .............................................................................. 74

USB Rise and Fall Times ........................................................................................................... 74

USB Jitter ................................................................................................................................... 75

USB EOP Width ......................................................................................................................... 75

SMBus Transaction .................................................................................................................... 75

SMBus Time-out ......................................................................................................................... 75

Power Sequencing and Reset Signal Timings ........................................................................... 76

1.8 V/3.3 V Power Sequencing................................................................................................... 76

C0 to C2 to C0 Timings .............................................................................................................. 76

Test Mode Entry (XOR Chain Example)..................................................................................... 77

Example XOR Chain Circuitry .................................................................................................... 78

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