AD9958SLASHPCB datasheet(27/40 Pages) AD

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AD9958

Rev. 0 | Page 27 of 40

SYNCHRONIZING MULTIPLE AD9958 DEVICES

The AD9958 allows easy synchronization of multiple AD9958

devices. At power-up the phase of SYNC_CLK can be offset

between multiple devices. To correct for the offset and align the

SYNC_CLK edges, there are three methods (one automatic

mode and two manual modes) of synchronizing SYNC_CLKs.

These modes force the internal state machines of multiple

devices to a known state, which aligns SYNC_CLKs.

Any mismatch in REF_CLK phase between devices results in a

corresponding phase mismatch on the SYNC_CLKs.

AUTOMATIC MODE SYNCHRONIZATION

In automatic mode, multiple part synchronization is achieved

by connecting the SYNC_OUT pin on the master device to the

SYNC_IN pin of the slave device(s). Devices are configured as

master or slave through programming bits, accessible via the

serial port.

A configuration for synchronizing multiple AD9958/59 devices

in automatic mode is shown in the Application Circuits section.

In this configuration, the AD9510 provides coincident

REF_CLKs and SYNC_OUTs to all devices.

Operation

The first step is to program the master and slave devices for

their respective roles. Enabling the master device is performed

by writing its master enable bit (FR2 <6>) true. This causes the

SYNC_OUT of the master device to output a pulse that has a

pulse width equal to one system clock period and a frequency

equal to one fourth of the system clock frequency. Enabling

device(s) as slaves is performed by writing the slave enable bit

(FR2 <7>) true.

In automatic synchronizing mode, the slave device(s) sample

SYNC_OUT pulses from the master device and a comparison of

all state machines is made by the autosynchronization circuitry.

If the slave device(s) state machines are not identical to the

master, the slave device(s) state machines are stalled for one

system clock cycle. This procedure synchronizes the slave

device(s) within three SYNC_CLK periods.

Delay Time Between SYNC_OUT and SYNC_IN

When the delay between SYNC_OUT and SYNC_IN exceeds

one system clock period, phase offset bits (FR2 <1:0>) are used

to compensate. The default state of these bits is 00, which

implies that the SYNC_OUT of the master and the SYNC_IN of

the slave have a propagation delay of less than one system clock

period. If the propagation time is greater than one system clock

period, the time should be measured and the appropriate offset

programmed. Table 24 describes the delays required per system

clock offset value.

Table 24.

System Clock

Offset Value

SYNC_OUT/SYNC_IN

Propagation Delay

0 ≤ delay ≤ 1

1 ≤ delay ≤ 2

2 ≤ delay ≤ 3

3 ≤ delay ≤ 4

Automatic Synchronization Status Bits

If a slave device falls out of sync, the sync status bit is set high.

This bit can be read through the serial port bit (FR2 <5>). It is

automatically cleared when read.

The synchronization routine continues to operate regardless of

the state of the status bit. The status bit can be masked by

writing Logic 1 to the synchronization status mask bit

(FR2 <4>). If the status bit is masked, it is held low.

MANUAL SOFTWARE MODE SYNCHRONIZATION

The manual software mode is enabled by setting the manual

synchronization bit (FR1 <0>) to Logic 1 in a device. In this

mode, the I/O update that writes the Manual SW synchro-

nization bit to Logic 0 stalls the state machine of the clock

generator for one system clock cycle. Stalling the clock

generation state machine by one cycle changes the phase

relationship of SYNC_CLK between devices by one system

clock period (90°).

Note that the user may have to repeat this process until the

devices have their SYNC_CLK signals in phase. The SYNC_IN

input may be left floating since it has an internal pull-up. The

SYNC_OUT is not used.

The synchronization is complete when the master and slave(s)

devices have their SYNC_CLK signals in phase.

MANUAL HARDWARE MODE SYNCHRONIZATION

Manual hardware mode is enabled by setting the manual SW

synchronization bit (FR1 <1>) to Logic 1 in a device. In manual

HW synchronization mode, the SYNC_CLK stalls by one

system clock cycle each time a rising edge is detected on the

SYNC_IN input. Stalling SYNC_CLK’s state machine by one

cycle changes the phase relationship of SYNC_CLK between

devices by one system clock period (90°).

Note that the user may have to repeat the process until the

devices have their SYNC_CLK signals in phase. The SYNC_IN

input might be left floating since it has an internal pull-up. The

SYNC_OUT is not used.

The synchronization is complete when the master and slave(s)

devices have their SYNC_CLK signals in phase.

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