AD9958SLASHPCB datasheet(38/40 Pages) AD

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AD9958

Rev. 0 | Page 38 of 40

CFR <4> = 0 (default). A new delta word is applied to the input,

as in normal operation, but not loaded into the accumulator.

CFR <4> = 1. This bit automatically synchronously clears (loads

0s) the sweep accumulator for one cycle upon reception of the

I/O_UPDATE sequence indicator.

CFR <5> match pipe delays active.

CFR <5> = 0 (default), match pipe delay mode is inactive.

CFR <5> = 1, match pipe delay mode is active. See the Single-

Tone Mode—Matched Pipeline Delay section for details.

CFR <6> DAC power-down.

CFR <6> = 0 (default). The DAC is enabled for operation.

CFR <6> = 1. The DAC is disabled and is in its lowest power

dissipation state.

CFR <7>. digital power-down.

CFR <7> = 0 (default). The digital core is enabled for operation.

CFR <7> = 1. The digital core is disabled and is in its lowest

power dissipation state.

CFR <8:9>. DAC LSB control.

CFR <8:9> = 00 (default). The DAC is at the largest LSB value.

CFR <10> must be set to 0.

CFR <13>.linear sweep ramp rate load at I/O_UPDATE.

CFR <13> = 0 (default). The linear sweep ramp rate timer is

loaded only upon timeout (timer =1) and is not loaded because

of an I/O_UPDATE input signal.

CFR <13> = 1. The linear sweep ramp rate timer is loaded upon

timeout (timer =1) or at the time of an I/O_UPDATE input

signal.

CFR <14> linear sweep enable.

CFR <14> = 0 (default). The linear sweep capability of the

AD9958 is inactive. CFR <14> = 1. The linear sweep capability

of the AD9958 is enabled. When enabled, the delta frequency

tuning word is applied to the frequency accumulator at the

programmed ramp rate.

CFR <15> linear sweep no-dwell.

CFR <15> = 0 (default). The linear sweep no-dwell function is

inactive. CFR <15> = 1. The linear sweep no-dwell function is

active. If CFR <15> is active, the linear sweep no-dwell function

is activated. See the Linear Sweep (Shaped) Modulation Mode

section for details. If CFR <14> is clear, this bit is don’t care.

CFR <18:16> open.

CFR <23:22> amplitude frequency phase select controls what

type of modulation is to be performed for that channel. See the

Modulation Mode section for details.

Channel Frequency Tuning Word (CFTWO) Description

CFTW0 <32:0> Frequency Tuning Word 0 for each channel.

Channel Phase Offset Word (CPOW) Description

CPO0 <13:0> Phase Offset Word 0 for each channel.

CPO0 <15:14> open.

Amplitude Control Register (ACR) Description

ACR <9:0> amplitude scale factor for each channel.

ACR <10> amplitude ramp rate load control bit.

ACR <10> = 0 (default). The amplitude ramp rate timer is

loaded only upon timeout (timer = 1) and is not loaded due to a

I/O_UPDATE input signal (or change in the profile bits).

ACR <10> = 1. The amplitude ramp rate timer is loaded upon

timeout (timer =1) or at the time of an I/O_UPDATE input

signal (or change in PS bits).

ACR <11> auto RU/RD enable (only valid when ACR <12> is

active high).

ACR <11> = 0 (default). When ACR <12> is active, Logic 0 on

ACR <11> enables the manual RU/RD operation. ACR <11> = 1.

If ACR <12> is active, a Logic 1 on ACR <11> enables the

AUTO RU/RD operation. See the Output Amplitude Control

Mode section of this document for details.

ACR <12> amplitude multiplier enable.

ACR <12> = 0 (default). Amplitude multiplier is disabled. The

clocks to this scaling function (auto RU/RD) are stopped for

power saving and the data from the DDS core is routed around

the multipliers.

ACR <12> = 1, amplitude multiplier is enabled.

ACR <13> open.

ACR <15:14> amplitude increment/decrement step size.

ACR <23:16> amplitude ramp rate value.

Channel Linear Sweep Register (LSR) Description

LSR <15:0> linear sweep rising ramp rate.

Channel Linear Sweep Rising Delta Word Register (RDW)

Description

RDW <31:0> 32-bit rising delta tuning word.

Channel Linear Sweep Falling Delta Word Register

(FDW) Description

FDW <31:0> 32-bit falling delta tuning word.

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