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AD9958

Rev. 0 | Page 29 of 40

SERIAL I/O PORT

OVERVIEW

The AD9958 serial I/O port offers multiple configurations to

provide significant flexibility. The serial I/O port offers an SPI-

compatible mode of operation that is virtually identical to the

SPI operation found in earlier Analog Devices DDS products.

The flexibility is provided by four data (SDIO_0:3) pins that

allow four programmable modes of serial I/O operation.

Three of the four data pins (SDIO_1:3) can be used for other

functions than serial I/O port operation. These pins can also be

used to initiate a ramp-up or ramp-down (RU/RD) of the 10-bit

amplitude output scalar. In addition, one of these pins

(SDIO_3) can also be used to provide the SYNC_I/O function

that resynchronizes the serial I/O port controller if it is out of

proper sequence.

The maximum speed of the serial I/O port SCLK is 200 MHz,

but the four data (SDIO_0:3) pins can be used to further

increase data throughput. The maximum data throughput using

all SDIO_0:3 pins is 800 Mbps.

Note that both channels share Registers 0x03 to 0x18, which are

shown in the Register Map section. This address sharing

enables both DDS channels to be written to simultaneously. For

example, if a common frequency tuning word is desired for

both channels, it can be written once through the serial I/O port

to both channels. This is the default mode of operation (both

channels enabled). To enable each channel to be independent,

the two channel enable bits found in the channel select register

(CSR) must be used.

There are effectively two sets or copies of addresses (0x03 to

0x18) that channel enable bits can access to provide channel

independence. See the Control Register Descriptions section for

further discussion of programming channels that are common

or independent from each other.

Serial operation of the AD9958 occurs at the register level, not

the byte level. That is, the controller expects that all byte(s)

contained in the register address are accessed. The SYNC_I/O

function can be used to abort an I/O operation, thereby

allowing fewer than all bytes to be accessed. This feature can be

used to program only a part of the addressed register. Note that

only completed bytes are affected.

There are two phases to a serial communications cycle. Phase 1

is the instruction cycle, which writes the instruction byte into

the AD9958. Each bit of the instruction byte is registered on

each corresponding rising edge of SCLK. The instruction byte

defines whether the upcoming data transfer is either a write or

read operation and contains the serial address of the address

Phase 2 of the I/O cycle consists of the actual data transfer

(write/read) between the serial port controller and the serial

port buffer. The number of bytes transferred during this phase

of the communication cycle is a function of the register being

accessed. The actual number of additional SCLK rising edges

required for the data transfer and instruction byte depends on

the number of byte(s) in the register and the serial I/O mode of

operation.

For example, when accessing Function Register 1, (FR1) which

is three bytes wide, Phase 2 of the I/O cycle requires that three

bytes be transferred. After transferring all data bytes per the

instruction byte, the communication cycle is completed for that

At the completion of a communication cycle, the AD9958 serial

port controller expects the next set of rising SCLK edges to be

the instruction byte for the next communication cycle. All data

written to the AD9958 is registered on the rising edge of SCLK.

Data is read on the falling edge of SCLK. See Figure 36 and

Figure 37.

Each set of communication cycles does not require an

I/O_UPDATE to be issued. The I/O_UPDATE transfers data

from the I/O port buffer to active registers. The I/O_UPDATE

can be sent for each communication cycle or can be sent when

all serial operations are complete. However, data is not active

until an I/O_UPDATE is sent, with the exception of the channel

enable bits in the Channel Select Register (CSR). These bits do

not require an I/O_UPDATE to be enabled.

tPRE

tDSU

tSCLK

tSCLKPWL

tSCLKPWH

tDHLD

SCLK

SDIO

SYMBOL

DEFINITION

tPRE

CS SETUP TIME

tSCK

PERIOD OF SERIAL DATACLOCK

tSCLKPWH

SERIAL DATA SETUP TIME

tSCLKPWL

SERIAL DATA CLOCK PULSE WIDTH HIGH

tDHLD

SERIAL DATA CLOCK PULSE WIDTH LOW

tDSU

SERIAL DATA HOLD TIME

MIN

1.0ns

2.2ns

5.0ns

2.2ns

1.6ns

0ns

Figure 40. Setup and Hold Timing for the Serial I/O Port

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