AD9958

Rev. 0 | Page 28 of 40

I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK

RELATIONSHIPS

The I/O UPDATE is essentially over sampled by the

SYNC_CLK. Therefore, I/O_UPDATE must have a

minimum pulse width greater than one SYNC_CLK period.

I/O_UPDATE and SYNC_CLK are used together to transfer

data from the serial I/O buffer to the active registers in the

device. Data in the buffer is inactive.

The timing diagram shown in Figure 39 depicts when data in

the buffer is transferred to the active registers.

SYNC_CLK is a rising edge active signal. It is derived from

the system clock and a divide-by-4 frequency divider. The

SYNC_CLK is externally provided, which can be used to

synchronize external hardware to the AD9958’s internal clocks.

I/O_UPDATE initiates the start of a buffer transfer. It can be

sent synchronously or asynchronous relative to the SYNC_CLK.

If the set-up time between these signals is met, then constant

latency (pipeline) to the DAC output exists. For example, if

repetitive changes to phase offset via the SPI port are desired,

the latency of those changes to the DAC output is constant,

otherwise a time uncertainty of 1 SYNC_CLK period is present.

SYNC_CLK

SYSCLK

AB

DATA 2

DATA 3

DATA 1

DATA IN

REGISTERS

DATA IN

I/O BUFFERS

DATA 1

DATA 2

DATA 3

I/O UPDATE

THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.

Figure 39.