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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9958/PCB датащи(PDF) 6 Page - Analog Devices |
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AD9958/PCB датащи(HTML) 6 Page - Analog Devices |
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6 / 40 page  AD9958 Rev. 0 | Page 6 of 40 Parameter Min Typ Max Unit Test Conditions/Comments Residual Phase Noise @ 15.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 20× @ 1 kHz Offset –127 dBc/Hz @ 10 kHz Offset –136 dBc/Hz @ 100 kHz Offset –139 dBc/Hz @ 1 MHz Offset –138 dBc/Hz Residual Phase Noise @ 40.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 20× @ 1 kHz Offset –117 dBc/Hz @ 10 kHz Offset –128 dBc/Hz @ 100 kHz Offset –132 dBc/Hz @ 1 MHz Offset –130 dBc/Hz Residual Phase Noise @ 75.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 20× @ 1 kHz Offset –110 dBc/Hz @ 10 kHz Offset –121 dBc/Hz @ 100 kHz Offset –125 dBc/Hz @ 1 MHz Offset –123 dBc/Hz Residual Phase Noise @ 100.3 MHz (fOUT) w/REF_CLK Multiplier Enabled 20× @ 1 kHz Offset –107 dBc/Hz @ 10 kHz Offset –119 dBc/Hz @ 100 kHz Offset –121 dBc/Hz @ 1 MHz Offset –119 dBc/Hz SERIAL PORT TIMING CHARACTERISTICS Maximum Frequency Serial Clock (SCLK) 200 MHz Minimum SCLK Pulse Width Low (tPWL) 1.6 ns Minimum SCLK Pulse Width High (tPWH) 2.2 ns Minimum Data Set-Up Time (tDS) 2.2 ns Minimum Data Hold Time 0 ns Minimum CSB Set-Up Time (tPRE) 1.0 ns Minimum Data Valid Time for Read Operation 12 ns MISCELLANEOUS TIMING CHARACTERISTICS Master_Reset Minimum Pulse Width 1 Min pulse width = 1 sync clock period I/O_Update Minimum Pulse Width 1 Min pulse width = 1 sync clock period Minimum Set-Up Time (I/O_Update to SYNC_CLK) 4.8 ns Rising edge to rising edge Minimum Hold Time (I/O_Update to SYNC_CLK) 0 ns Rising edge to rising edge Minimum Set-Up Time (Profile Inputs to SYNC_CLK) 5.4 ns Minimum Hold Time (Profile Inputs to SYNC_CLK) 0 ns Minimum Set-Up Time (SDIO Inputs to SYNC_CLK) 2.5 ns Minimum Hold Time (SDIO Inputs to SYNC_CLK) 0 ns Propagation Time Between REF_CLK and SYNC_CLK 2.25 3.5 5.5 ns CMOS LOGIC INPUTS VIH 2.0 V VIL 0.8 V Logic 1 Current 3 12 µA Logic 0 Current −12 µA Input Capacitance 2 pF CMOS LOGIC OUTPUTS (1 mA Load) VOH 2.7 V VOL 0.4 V POWER SUPPLY Total Power Dissipation —Both Channels On, Single- Tone Mode 315 380 mW Dominated by supply variation Total Power Dissipation —Both Channels On, with Sweep Accumulator 350 420 mW Dominated by supply variation Total Power Dissipation —Full Power Down 13 mW IAVDD —Both Channels On, Single Tone Mode 90 105 mA |
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