AD9958SLASHPCB datasheet(37/40 Pages) AD

37 / 40 page

AD9958

Rev. 0 | Page 37 of 40

The RU/RD bits control the amplitude RU/RD time of a

channel (see the Output Amplitude Control Mode section).

FR1 <12:14> profile pin configuration bits.

The profile pin configuration bits control the configuration of

the data and SDIO pins for the different modulation modes. See

the Modulation Mode section for details.

FR1 <15> open.

FR1 <17:16> charge pump current control.

FR1 <17:16> = 00 (default), the charge pump current is 75 µA.

= 01 charge pump current is 100 µA.

= 10 charge pump current is 125 µA.

= 11 charge pump current is 150 µA.

FR1 <22:18> PLL divider values.

FR1 <22:18>, if the value is > 3 and < 21, the PLL is enabled and

the value sets the multiplication factor. If the value is < 4 or >20

the PLL is disabled.

FR1 <23> PLL VCO gain.

FR1 <23> = 0 (default), the low range (system clock below

160 MHz). FR1 <23> = 1, the high range (system clock above

255 MHz).

Function Register 2 (FR2) Description

The FR2 is comprised of two bytes located in Address 0x02.

The FR2 is used to control the various functions, features, and

modes of the AD9958. The functionality of each bit is detailed

as follows:

FR2<1:0> system clock offset.

See the Synchronizing Multiple AD9958 Devices section for

more details.

FR2 <3:2> open.

FR2 <4> multi-device synchronization mask bit.

FR2 <5> multi-device synchronization status bit.

FR2 <6> multi-device synchronization master enable bit.

FR2<7> multi-device synchronization slave enable bit.

FR2 <4:7>. see the Synchronizing Multiple AD9958 Devices

section for more details.

FR2 <11:8> open.

FR2 <12> both channels clear phase accumulator.

FR2 <12> = 0 (default), the phase accumulator functions as

normal. FR2 <12> = 1, the phase accumulator memory

elements for both channels are asynchronously cleared.

FR2 <13> both channels auto clear phase accumulator.

FR2 <13> = 0 (default). A new frequency tuning word is applied

to the inputs of the phase accumulator, but not loaded into the

accumulator.

FR2 <13> = 1. This bit automatically synchronously clears

(loads zeros into) the phase accumulator for one cycle upon

reception of the I/O update sequence indicator on both

channels.

FR2 <14> both channels clear sweep accumulator.

FR2 <14> = 0 (default), the sweep accumulator functions as

normal.FR2 <14> = 1, the sweep accumulator memory

elements for both channels are asynchronously cleared.

FR2 <15> both channels auto clear sweep accumulator.

FR2 <15> = 0 (default). A new delta word is applied to the

input, as in normal operation, but not loaded into the accumu-

lator. FR2 <15> = 1. This bit automatically synchronously clears

(loads 0s) the sweep accumulator for one cycle upon reception

of the I/O_UPDATE sequence indicator on both channels.

CHANNEL FUNCTION REGISTER (CFR)

DESCRIPTION

CFR <0> enable sine output.

CFR <0> = 0 (default). The angle-to-amplitude conversion logic

employs a cosine function. CFR <0> = 1. The angle-to-

amplitude conversion logic employs a sine function.

CFR <1> clear phase accumulator.

CFR <1> = 0 (default). The phase accumulator functions as

normal. CFR <1> = 1. The phase accumulator memory

elements are asynchronously cleared.

CFR <2> clear phase accumulator.

CFR <2> = 0 (default). A new frequency tuning word is applied

to the inputs of the phase accumulator, but not loaded into the

accumulator. CFR <2> = 1. This bit automatically synchro-

nously clears (loads 0s) the phase accumulator for one cycle

upon reception of the I/O_UPDATE sequence indicator.

CFR <3> clear frequency accumulator.

CFR <3> = 0 (default). The sweep accumulator functions as

normal .CFR <3> = 1. The sweep accumulator memory

elements are asynchronously cleared.

CFR <4> auto clear sweep accumulator.

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