AD9958SLASHPCB datasheet(20/40 Pages) AD

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AD9958

Rev. 0 | Page 20 of 40

REF_CLK

PIN 23

25MHz

XTAL

REF_CLK

PIN 22

22pF

Figure 34.

SCALABLE DAC REFERENCE CURRENT CONTROL

MODE

The RSET is common to both DACs. As a result, the full-scale

currents are equal as a default. The scalable DAC reference can

be used to set each DAC’s full-scale current independently from

one another. This is accomplished by using the CFR register bits

<9:8>. Table 5 shows how each DAC can be individually scaled

for independent channel control. This provides for binary

attenuation.

Table 5.

CFR <9:8>

LSB Current State

Full scale

Half scale

Quarter scale

Eighth scale

POWER-DOWN FUNCTIONS

The AD9958 supports an externally controlled power-down

feature and the more common software programmable power-

down bits found in previous Analog Devices DDS products.

The software control power down allows the input clock

circuitry, DAC, and the digital logic (for each separate channel)

to be individually powered down via unique control bits

(CFR <7:6>). These bits are not active when the externally

controlled power-down pin (PWR_DWN_CTL) is high. When

the PWR_DWN_CTL input pin is high, the AD9958 enters a

power-down mode based on the FR1 <6> bit. When the

PWR_DWN_CTL input pin is low, the external power-down

control is inactive.

When the FR1 <6> bit is zero, and the PWR_DWN_CTL input

pin is high, the AD9958 is put into a fast recovery power-down

mode. In this mode, the digital logic and the DACs digital logic

are powered down. The DACs bias circuitry, oscillator, and

clock input circuitry is not powered down.

When the FR1 <6> bit is high and the PWR_DWN_CTL pin is

high, the AD9958 is put into the full power-down mode. In this

mode, all functions are powered down. This includes the DACs

and PLL, which take a significant amount of time to power up.

When the PLL is bypassed, the PLL is shut down to conserve

power.

When the PWR_DWN_CTL input pin is high, the individual

power down bits (CFR <7:6>) and FR1 <7>) are invalid (don’t

care) and are unused. When the PWR_DWN_CTL input pin is

low, the individual power-down bits control the power-down

modes of operation.

Note that the power-down signals are all designed such that a

Logic 1 indicates the low power mode and Logic 0 indicates the

powered-up mode.

MODULATION MODE

The AD9958 can perform 2-/4-/8- or 16-level modulation of

frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is

achieved by applying data to the profile pins. Each channel can

be programmed separately, but the ability to modulate both

channels simultaneously is constrained by the limited number

of profile pins. For instance, 16-level modulation uses all four

profile pins, which inhibits modulation for the remaining

channel.

In addition, the AD9958 has the ability to ramp up or ramp

down the output amplitude before, during, or after a

modulation (FSK, PSK only) sequence. This is performed by

using the 10-bit output scalar. If the RU/RD feature is desired,

unused profile pins or unused SDIO_1:3 pins can be configured

to initiate the operation. See the Output Amplitude Control

Mode section for more details of the RU/RD feature.

In modulation mode, each channel has its own set of control

bits to determine the type (frequency, phase, or amplitude) of

modulation. Each channel has 16 profile registers for flexibility.

modulation of frequency, phase, or amplitude. Registers 0x04,

0x05, and 0x06 are dedicated registers for frequency, phase, and

amplitude, respectively. These registers contain the first

frequency, phase offset, and amplitude word.

Frequency modulation has a 32-bit resolution, phase modula-

tion is 14 bits, and amplitude is 10 bits. When modulating phase

or amplitude, the word value must be MSB-aligned in the

profile registers and the unused bits are don’t care bits.

In modulation mode, AFP bits (CFR <23:22>) and level bits

(FR1 <9:8>) are programmed to configure the modulation type

and level. See Table 6 and Table 7 settings. Note that the linear

sweep enable bit must be set to Logic 0 in direct modulation

mode.

Table 6.

AFP CFR

<23:22>

Linear Sweep

Enable CFR <14>

Description

Modulation disabled

Amplitude modulation

Frequency modulation

Phase modulation

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