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AD9958/PCB датащи(PDF) 31 Page - Analog Devices

номер детали AD9958/PCB
подробное описание детали  2-Channel 500 MSPS DDS with 10-Bit DACs
PDF  40 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD9958/PCB датащи(HTML) 31 Page - Analog Devices

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AD9958
Rev. 0 | Page 31 of 40
SERIAL I/O MODES OF OPERATION
The following are the four programmable modes of the serial
I/O port operation:
1.
Single bit serial 2-wire mode (default mode).
2.
Single bit serial 3-wire mode.
3.
2-bit serial mode.
4.
4-bit serial mode (SYNC_I/O not available).
Table 6 displays the function of all six serial I/O interface pins,
depending on the mode of serial I/O operation programmed.
Table 26. Serial I/O Port Pin Function vs. Serial I/O Mode
Pin
Name
Single Bit
Serial 2-Wire
Mode
Single Bit
Serial 3-Wire
Mode
2-Bit
Serial
Mode
4-Bit
Serial
Mode
SCLK
Serial
Serial
Serial
Serial
Clock
Clock
Clock
Clock
CSB
Chip Select
Chip Select
Chip
Select
Chip
Select
SDIO_0
Serial Data
I/O
Serial Data In
Serial
Data I/O
Serial
Data
I/O
SDIO_1
Not used for
SDIO1
Not used for
SDIO1
Serial
Data I/O
Serial
Data
I/O
SDIO_2
Not used for
SDIO1
Serial Data
Out (SDO)
Not used
for SDIO1
Serial
Data
I/O
SDIO_3
SYNC_I/O
SYNC_I/O
SYNC_I/O
Serial
Data
I/O
1In serial mode, these pins can be used for RU/RD operation
.
The two bits CSR <2:1> in the channel select register set the
serial I/O mode of operation are defined as follows:
CSR <2:1> = 00. Single bit serial mode (2-wire mode).
CSR <2:1> = 01. Single bit serial mode (3-wire mode).
CSR <2:1> = 10. 2-bit serial mode.
CSR <2:1> = 11. 4-bit serial mode.
Single Bit Serial (2- and 3-Wire) Modes
The single bit serial mode interface allows read/write access to
all registers that configure the AD9958. MSB-first or LSB-first
transfer formats are supported. In addition, the single bit serial
mode interface port can be configured as either a single pin I/O,
which allows a two-wire interface or two unidirectional pins for
in/out, which enable a 3-wire interface. Single bit mode allows
the use of the SYNC_I/O function.
In single-bit serial mode, 2-wire interface operation, the
SDIO_0 pin is the single serial data I/O pin. In single-bit serial
mode 3-wire interface operation, the SDIO_0 pin is the serial
data input pin and the SDIO_2 pin is the output data pin.
Regardless of the number of wires used in the interface, the
SDIO_3 pin is configured as an input and operates as the
SYNC_I/O pin in the single-bit serial mode and 2-bit serial
mode. The SDIO_1 pin is unused in this mode. See Table 26.
2-Bit Serial Mode
The SPI port operation in 2-bit serial mode is identical to the
SPI port operation in single bit serial mode, except that two bits
of data are registered on each rising edge of SCLK. Therefore, it
only takes four clock cycles to transfer eight bits of information.
The SDIO_0 pin contains the even numbered data bits using
the notation D <7:0> and the SDIO_1 pin contains the odd
numbered data bits. This even and odd numbered pin/data
alignment is valid in both MSB- and LSB-first formats (see
Figure 39).
4-Bit Serial Mode
The SPI port in 4-bit serial mode is identical to the SPI port in
single bit serial mode, except that four bits of data are registered
on each rising edge of SCLK. Therefore, it only takes two clock
cycles to transfer eight bits of information. The SDIO_0 and
SDIO_2 pins contain even numbered data bits using the
notation D <7:0> and the SDIO_0 pin contains the LSB of the
nibble. The SDIO_1 and SDIO_3 pins contain the odd
numbered data bits and the SDIO_1 pin contains the LSB of the
nibble to be accessed.
Note that when programming the device for 4-bit serial mode,
it is important to keep the SDIO_3 pin at Logic 0 until the
device is programmed out of the single bit serial mode. Failure
to do so can result in the serial I/O port controller being out of
sequence.
Figure 42 through Figure 44 represent write timing diagrams
for each serial I/O modes available. Both MSB and LSB-first
modes are shown. LSB-first bits are shown in parenthesis. The
clock stall low/high feature shown is not required. It is used to
show that data (SDIO) must have the proper setup time relative
to the rising edge of SCLK.



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