AD9958

Rev. 0 | Page 15 of 40

AD9958

(SLAVE 1)

AD9958

(MASTER)

CLOCK

SOURCE

AD9958

(SLAVE 2)

AD9958

(SLAVE 3)

REF_CLK

FPGA

DATA

SYNC_CLK

FPGA

DATA

SYNC_CLK

FPGA

DATA

SYNC_CLK

FPGA

DATA

SYNC_CLK

C1

S1

C2

S2

C3

S3

C4

S4

A1

A2

A4

A3

A_END

CENTRAL

CONTROL

AD9510

CLOCK DISTRIBUTOR

WITH

DELAY EQUALIZATION

SYNC_IN

SYNC_OUT

AD9510

SYNCHRONIZATION

DELAY EQUALIZATION

Figure 27. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and SYNC Clock

ACOUSTIC OPTICAL

TUNABLE FILTER

OPTICAL FIBER CHANNEL

W/MULITIPLE DISCRETE

WAVELENGTHS

OUTPUTS

INPUTS

SELECTABLE WAVELENGTH FROM EACH

CHANNEL VIA DDS TUNING AOTF

SPLITTER

WDM

SOURCE

WDM SIGNAL

CH 0

CH 1

CH 0 CH 1

CH 0

CH 1

AD9958

REF CLK

AMP

AMP

Figure 28. DDS Providing Stimulus for Acoustic Optical Tunable Filter